Gennum Corporation

Blackberry Corporation

Paratek Microwave Incorporated

Andrew V Cervin-Lawry

Atin J Patel

Mark Vandermeulen

Ivoyl Koutsaroff

Mircea Capanu

James D Kendall

Marina Zelner

David Kinsey

Petrus T Appelman

Efim Roubakha

Luigi Di Pede

Luigi DiPede

In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

Method of forming a multi-level thin film capacitor

A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Electrostrictive resonance suppression for tunable capacitors

Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same

In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of: depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned mask layer over the polysilicon film, such that the polysilicon film includes masked and unmasked portions; etching the unmasked portions of the polysilicon film for a first amount of time; oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that defines the patterned polysilicon layer; and removing the patterned mask layer; wherein the first and second amounts of time are selected such that the oxide layer and the patterned polysilicon layer have about the same thickness and form a planar surface.

Local oxidation of silicon planarization for polysilicon layers under thin film structures

Multi-level thin film capacitor on a ceramic substrate

An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivity type, a channel region of second conductivity type separating the first and second injector regions and a first electrically floating structure disposed above the channel region, wherein a first edge portion of the floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of the second injector region, and a control gate region of fourth conductivity type located within the second conductivity type semiconductor substrate region. The gate structure and first floating structure are electrically connected together. In different aspects of the present invention, the EEPROM memory cell may also include a second capacitor.

Low voltage single poly deep sub-micron flash EEPROM

Low voltage single poly deep sub-micron flash eeprom

An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor. The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic steps, resulting in a lower and better controlled programming voltage, programming energy and ON state resistance. Typically the conductive filament formed in the new antifuse is about 0.65 microns long and is formed by a voltage pulse having a relatively slow rise time (e.g. 150 microseconds), resulting in improved properties which provide advantages in circuit design and in manufacturing circuits using the new antifuse.

Method of making antifuse based on silicided single polysilicon bipolar

Growing community of inventors

Crescent, Canada

Andrew V Cervin-Lawry