Motorola Corporation

Andrew Tomerlin

Robert E Stengel

Nicholas Giovanni Cafaro

Robert Stephens

Asad U Aman

A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line () having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of F. A second delay line () also receives the reference clock at an input. A logic circuit () combines signals from the delay line taps of the first delay line () with signals from the delay line taps of the second and/or first delay line () to produce a collection of clock pulses having a combined clock rate of F*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register () contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.

Delay line based multiple frequency generator circuits for CDMA processing

A reconfigurable processor circuit () consistent with certain embodiments of the present invention has an array of configurable circuit blocks (), wherein certain of the configurable circuit blocks () comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor () configures a function of a plurality of the configurable circuit blocks. A memory () stores program instructions used by the control processor (). A multiple frequency generator () receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (). A timing control circuit () receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit () operates under control of the control processor ().

Reconfigurable processing circuit including a delay locked loop multiple frequency generator for generating a plurality of clock signals which are configured in frequency by a control processor

A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (), where N is an integer greater than one. N frequency extender circuits () receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers () produce N seed update values. A plurality of N seed registers () each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits () each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits () produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Multiple user reconfigurable CDMA processor

A predistortion linear power amplifier utilizes several predistortion computation engines to receive a first carrier signal. The predistortion computation engines also receive input from a predistortion algorithm engine. The predistortion algorithm engine receives its data from a predistortion amplifier sensor that monitors the operating characteristics of the amplifier and also from a feedback control circuit that provides frequency correlated input and feedback data. The processed data from the predistortion algorithm engine is then input into the predistortion computation engine along with the carrier signal. An output combiner circuit takes the output of each predistortion computation engine and generates a single correction estimate, which is then input into the nonlinear amplifier for producing a substantially linear output signal.

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Coral Springs, FL, United States of America

Andrew Tomerlin