Intel Corporation

Oculus, Vr, LLC

Facebook Technologies, LLC

Andrew Thomas Forsyth

Jonathan Cannon Hall

Christopher J Hughes

Brian J Hickmann

Edward Thomas Grochowski

Lisa K Wu

Dennis Ryan Bradford

Robert Dale Cavin

Robert Valentine

Bret L Toll

Jesus Corbal

Milind Baburao Girkar

Jeffrey G Wiedemeier

Elmoustapha Ould-Ahmed-Vall

Mark Jay Charney

Suleyman Sair

Seth Abraham

Charles R Yount

Jesus Corbal San Adrian

Sridhar Samudrala

James Charles Abel

Roger Espasa Sans

Santiago Galan Duran

Eric A Sprangle

Evan Mark Richards

Thomas D Fletcher

Ramacharan Sundararaman

Nirav Rajendra Patel

Ravi Rajwar

George Zacharias Chrysos

Joshua B Fryman

Roger Espasa

John Cruz Mejia

Jean-Luc Duprat

Yen-Kuang Chen

Shizhe Shen

Sailesh Kottapalli

Douglas M Carmean

Michael D Upton

Anwar Q Rohillah

Lyle David Bainbridge

Hideki Ido

Paul Albert Lalonde

Michael Abrash

Toni Juan

Mark Charney

Renju Thomas

Matthew J Craighead

Manel Fernandez

Robert C Valentine

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Coalescing adjacent gather/scatter operations

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Vector friendly instruction format and execution thereof

An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.

Processors having fully-connected interconnects shared by vector conflict instructions and permute instructions

Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks

Embodiments relate to a method and a system for performing image compression and decompression of image data. In one or more embodiments, the image data is divided into one or more image data blocks, and the image compression and decompression are performed for each image data block. The image data block is compressed and includes a base value corresponding to a first image component and a compressed difference value corresponding to a second image component. For decompression, a first value of the image data block can be obtained based on the base value, and a second value of the image data block can be obtained based on the first value, the first compressed difference value and a corresponding quantization table. An output image can be presented to a user, according to the decompressed image data block.

Display-side video decompression using quantization tables

According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.

Instructions for storing in general purpose registers one of two scalar constants based on the contents of vector write masks

A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

System and method for using a mask register to track progress of gathering and scattering elements between data registers and memory

An electronic display is driven to compensate for aging of pixels in the electronic display. An aging factor is determined based on initial display data for a display portion of the electronic display during one or more monitored frames. The aging factor is indicative of aging of pixels in the display portion of the electronic display due to use corresponding to the initial display data. An aging counter for the display portion is increased based on the determined aging factor. A compensation value is determined for the display portion based on the aging counter for the display portion. Input display data for the display portion is modified during a subsequent frame according the determined compensation value. The display portion is driven with the modified input display data during the subsequent frame.

Aging compensation for virtual reality headset display device

A method for correcting non-uniformities of one or more display panels of a HMD (e.g., a VR headset or an AR headset) is disclosed, where the method is based on a luminance level of content being displayed. The method includes obtaining the calibration data for correcting non-uniformity of a display panel of the HMD at various brightness levels and storing the data. In response to receiving a request for providing content to be presented on the HMD, the host applies the calibration data based on a luminance level of content being rendered to correct for any non-uniformities of the one or more display panels while rendering the content for display.

Luminance-based non-uniformity correction for display panels in head-mounted displays

Growing community of inventors

Kirkland, WA, United States of America

Andrew Thomas Forsyth