Dialog Semiconductor Gmbh

Morse Micro Pty. Ltd.

The Silanna Group Pty Ltd

Broadcom Corporation

Andrew Terry

Yashodhan Vijay Moghe

Andrew John Myles

Sebastian Loeda

Peter Bradley

Steven Grant Duvall

David Goodall

Andrew James Read

Michael De Nil

Sebastien Loeda

The disclosure is directed to a system and methods for waking-up a wireless receiver on a wireless network. The method includes the steps of: listening, by the wireless receiver, for signals in a predetermined frequency band periodically and decoding a wake-up key; validating the wake-up key by correlating the wake-up key with values stored in a memory using a first processing device; if the wake-up key is validated, decoding at least one PHY Protocol Data Unit (PPDU) and checking the value of one or more bits of the PPDU to validate the decoded PPDU as a wake-up PPDU; if the wake-up packet is validated, decoding a wake-up address and comparing the wake-up address to the station (STA) wake-up address; if the decoded wake-up address matches the STA wake-up address, powering-up a second processing device and confirming wake-up by exchanging an encrypted frame with Access Point (AP).

System and method for wireless receiver low-power wake-up in a wireless local area network

A radio frequency transmitter including two digital to analog converter circuits. The two radio frequency digital to analog converter circuits are configured to operate independently or operating in unison. Operating independently includes each radio frequency digital to analog converter circuit of the two radio frequency digital to analog converter circuits receiving separate baseband signals and separate local oscillation inputs. Operating in unison includes both of the two radio frequency digital to analog converter circuits receiving a single baseband signal and a single local oscillation input. The two radio frequency digital to analog converter circuits are configured to change between operating independently and operating in unison.

Programmable polar and cartesian radio frequency digital to analog converter

Various circuitry may benefit from appropriate matching. For example, certain low noise broadband amplifiers may benefit from resistive matching.

Low noise broadband amplifier with resistive matching

Single-chip multi-domain galvanic isolation device and method

An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.

Single-chip integrated circuit with capacitive isolation and method for making the same

A variable gain analog amplifier is described that uses pulse-density modulation in the form of a sigma-delta modulator (SDM) to produce a gain by modulating the selection of a switch that selects the amount of resistance in a negative feedback loop of the amplifier. The output of the SDM is dithered to increase the gain resolution of the analog amplifier, wherein the increased resolution produces a quiet, inaudible transition between changes in gain setting at an output of the variable gain amplifier and in addition produces a quiet, inaudible mixing and merging of audio signals.

Sigma-delta modulator approach to increased volume resolution in audio output stages

Communication processing paths include distortions, such as DC offset in the baseband analog path which needs to be accounted for. The use of a digital-to-analog converter (DAC) to inject a DC offset cancellation signal can bring about noise/area/power advantages. The DAC is driven by a mixed signal low pass filter loop. However, the DAC could also be driven in an open loop system, or a combination of open and closed loop. A low noise sign and magnitude DAC with low area and power requirements is implemented using selectively connected programmable current sources to virtual earth input terminals on a transimpedance amplifier (TIA) op-amp circuit. The constant virtual earth voltage eliminates linearity problems that would otherwise exist due to the finite current source output impedance. Current sources are only switched in when required so unneeded sources are out of circuit and do not contribute noise or use any power.

DC offset cancellation

Systems and methods to achieve an IC audio volume control requiring minimum silicon area and having an accurate volume control gain setting are disclosed. A resistive element in form of a R/2R ladder is deployed between an output node of an operational amplifier and an input node of the circuit. All resistors of said resistive element are unit resistors having a same resistance, wherein said unit resistors are arranged in parallel or series combinations to achieve a resistance desired. A first number of switches are deployed between nodes of the R/2R ladder and an inverting input of the operational amplifier. Furthermore a second number of switches are deployed between nodes within resistor units of the R/2R ladder and the inverting input. The circuit invented could have a single input or a differential input, or a single ended output or a differential output.

R/2R programmable gate array

Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

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Picton, Australia

Andrew Terry