International Business Machines Corporation

Globalfoundries Inc.

Institute for Information Technology Advancement

Andrew Tae Kim

Baozhen Li

Chih-Chao Yang

Ping-Chuan Wang

Ernest Y Wu

Ronald G Filippi

Erdem Kaltalioglu

Barry P Linder

Lijuan Zhang

Chengwen Pei

Joseph F Maniscalco

Timothy Dooling Sullivan

Andrew Herbert Simon

Griselda Bonilla

Junjing Bao

Minhua Lu

Fen Chen

Naftali Eliahu Lustig

Samuel S Choi

Cathryn Jeanne Christiansen

A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.

Fabrication of phase change memory cell in integrated circuit

A resistive random access memory (RRAM) device and a method for constructing the device is described. A capping layer structure is provided over a bottom contact where the capping layer includes a recess situated over the bottom contact. A first portion of the recess is filled with a lower electrode such that the width of the recess defines the width of the lower electrode. A second portion of the recess is filled with a high-K layer so that a bottom surface of the high-K layer has a stepped profile. A top electrode is formed on the high-K layer and a top contact is formed on the top electrode. The width of the high-K layer is greater than the width of the lower electrode to prevent shorting between the top contact and the lower electrode of the RRAM device.

Reliable resistive random access memory

A switchable metal insulator metal capacitor (MIMcap) and a method for fabricating the MIMcap. In another aspect of the invention operating the MIMcap is also described. A first capacitor plate and a second capacitor plate are separated by a capacitor dielectric and disposed over a substrate. A first via is electrically connected to the first capacitor plate and comprised of phase change material (PCM). The PCM is deposited in an electrically conductive state and convertible by application of heat to an insulating state. A first heater is proximate to and electrically isolated from the PCM in the first via. When the first heater is activated it converts the PCM in the first via to the insulating state. This isolates the first capacitor plate from an integrated circuit.

Switchable metal insulator metal capacitor

A void-less bottom electrode structure is formed at least partially in a via opening having a small feature size and containing a conductive landing pad structure which is composed of a metal-containing seed layer that is subjected to a reflow anneal. A metal-containing structure is located on a topmost surface of the bottom electrode structure. The metal-containing structure may be composed of an electrically conductive metal-containing material or a material stack of electrically conductive metal-containing materials. In some embodiments, the bottom electrode and the metal-containing structure collectively provide a non-volatile memory device.

Bottom electrode structure and method of forming the same

An e-Fuse device including a first electronic feature and a second electronic feature comprised of a conductive material, each of the first electronic feature and the second electronic feature having a width at least as great as a ground rule of a patterning process; and a fuse element comprised of the conductive material having a width less than the ground rule of the patterning process, the fuse element connecting a bottom portion of the first electronic feature and a bottom portion of the second electronic feature. Also disclosed is a method of making the e-Fuse device.

Sub-ground rule e-Fuse structure

An electrode structure is located at least partially in a via opening having a small feature size and containing a fuse element which is composed of a fuse element-containing seed layer that is subjected to a reflow anneal. The electrode structure is composed of a material having a higher electromigration (EM) resistance than the material that provides the fuse element. Prior to programming, the fuse element is present along sidewalls and a bottom wall of the electrode structure. After programming, a void is formed in the fuse element along at least one sidewall of the electrode structure and the resistance of the device will increase sharply.

BEOL electrical fuse

An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an 'insulator-to/from metal transition (IMT)' liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.

Advanced interconnects containing an IMT liner

An interconnection for a device in an integrated circuit includes a substrate on which a first metal line is embedded in a first dielectric layer. A via gouge is etched in the first metal line. A second dielectric layer is deposited over the first metal line and the first dielectric layer. A first via recess is etch through the second dielectric layer where the first via recess aligned to the via gouge. A second metal layer is deposited in the first via recess and the via gouge, forming a first via.

Fabricating vias with lower resistance

A mandrel structure includes a first mandrel, a second mandrel and a third mandrel in a parallel arrangement. The second mandrel is located between the first and third mandrels and has a cut larger than a minimum ground rule feature. A sidewall layer is formed over the mandrel structure. The sidewall layer has two long parallel gaps for two contact lines and a third gap for a fuse element. The third gap is orthogonal to and connects the two long parallel gaps. The sidewall pattern is used to form a trench structure comprising two parallel contact line trenches having a width at least as great as a ground rule of the patterning process for the contact lines and an orthogonal fuse element trench having a width less than the ground rule for the fuse element. A conductive material forms the contact lines and a fuse element.

Back end of the line precision resistors that allow for high currents and for configuration as an eFuse by embedding a single thin film high resistive metal material within a dielectric layer, wherein the resisters are coupled to sidewalls of adjacent metal interconnects are described. The resistors can be formed in the metal one (M1) dielectric layer and can be coupled to sidewalls of the M1 interconnects. Also described are processes for fabricating integrated circuits including the resistors and/or e-Fuses.

BEOL thin film resistor

A via and a method of fabricating a via in an integrated circuit involve forming a trench in dielectric material deposited above a first cap of a first metal level. The method includes patterning a collar from insulator material directly above the first cap, and etching through the first cap, within an area surrounded by the collar, to a first metal layer of the first metal level directly below the first cap. A liner is conformally deposited. The liner lines sidewalls of the collar. A metal conductor is deposited to form the via and a second metal layer of a second metal level.

Collar formation for chamfer-less and chamfered vias

A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.

Graded interconnect cap

A method and structure to isolate BEOL MIM capacitors shorted or rendered highly leaky due to in process, or service induced defects, in a semiconductor chip are provided such that the rejection and loss of yield of otherwise good chips is minimized. In one embodiment, the method incorporates an isolation element such as, for example, a fuse, or a phase change material such as, a metal/insulation transition metal material, in series between the MIM capacitor and the active circuit. When a high current passes through the element due to the MIM capacitor being defective, the isolation element is rendered highly resistive or electrically open thereby disconnecting the defective capacitor or electrode plate from the active circuitry.

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Poughkeepsie, NY, United States of America

Andrew Tae Kim