Lucent Technologies Inc.

Andrew T Schnable

Roman Antosik

Richard L Ukeiley

Lewis K Stroll

William R Krieg

Hemant Kumar KashinathRao Revankar

Babu Kalampukattussery Cherian

Shiva Kumar Yenigalla

Shreedhara Maduvinakodi Ramegowda

Multiple fiber channel (FC) storage area networks (SANs) are interconnected over wide-area networks (WANs) to form a long-distance (e.g., greater than about 10 km) distributed storage area network (DSAN) that includes FC to Internet Protocol (IP) over WAN (e.g., SONET or gigabit Ethernet (GE)) gateways that interwork the FC buffer-to-buffer and IP/WAN flow-control mechanisms appropriate to either the SONET or GE link layers using an additive increase, multiplicative decrease (AIMD) congestion avoidance algorithm. The gateways effectively spoof the FC buffer-to-buffer credit mechanism on the FC-interface side of the gateway, while using an IP Internet control message protocol (ICMP) quench mechanism on all WAN links and additionally the IEEE 802.3 pause packet flow control mechanism on gigabit Ethernet (GE) WAN links in combination, in both cases, with a rate-throttling mechanism at the FC&#x3c;-&#x3e;IP converter.

Flow control between fiber channel and wide area networks

Circuitry for a node of an optical communication network is configured to mux (i.e., combine) one or more incoming customer signals for transmission as a single outgoing optical signal and to demux (i.e., split) an incoming optical signal into one or more outgoing customer signals, where the muxing and demuxing clocks are selected from one or more customer clocks recovered from the one or more customer signals, an input clock recovered from the incoming optical signal, and a local clock generated by a local clock generator. When configured for an add/drop configuration, the circuitry selects (1) the muxing clock from the one or more customer clocks, the input clock, and the local clock and (2) the demuxing clock from the input clock and the local clock. When configured for a drop/continue configuration, the circuitry is configured to select both the muxing and demuxing clocks from either the first input clock or the local clock. The circuitry is configured to perform a hardware-based switch to select the backup clock as the new muxing clock upon detection of a loss-of-clock condition for the previously selected muxing clock. The node automatically coordinates its selection of muxing clocks with the other corresponding node in order to avoid loop-timing problems.

Timing circuitry for muxing/demuxing of optical communication signals

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Cary, NC, United States of America

Andrew T Schnable