Intel Corporation

Hiel Corporation

Andrew T Lauritzen

Altug Koker

Abhishek R Appu

David M Cimini

Gabor Liktor

Hugues Labbe

Tomasz Janczak

Louis Feng

Tomer Bar-On

John G Gierach

Joydeep Ray

Prasoonkumar Surti

Balaji Vembu

Travis T Schluessler

Nikos Kaburlasos

John H Feit

Jacek Kwiatkowski

Subramaniam M Maiyuran

Murali Ramadoss

Guei-Yuan Lueh

Karthik Vaidyanathan

Michael Apodaca

David M Puffer

Abhishek Venkatesh

Elmoustapha Ould-Ahmed-Vall

Devan Burke

Philip R Laws

Ankur N Shah

Kai Xiao

Atsuo Kuwahara

Jeffery S Boles

Jonathan Kennedy

Marco Salvi

Sameer Kp

Aaron Eliot Lefohn

Slawomir Grajewski

Kiril Vidimce

Jeffrey S Boles

David Puffer

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

Topology shader technology

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

Graphics with adaptive temporal adjustments

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.

Handling surface level coherency without reliance on fencing

Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading

An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

Tile-based immediate mode rendering with early hierarchical-z

Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.

Deferred geometry rasterization technology

Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.

Decoupled multi-layer render frequency

Growing community of inventors

Victoria, Canada

Andrew T Lauritzen