Unisys Corporation

Other

Andrew T Jennings

Charles R Caldarale

Kevin W Harris

Timothy Neilson Fender

Maurice Marks

William Stratton

G Lawrence Krablin

Craig R Church

Joseph S Schibinger

John A Keller

Duane J McCrory

Michael K Benton

David W Schroth

Brian Garrett

John L Janssen

Jospeh S Schibinger

Ronald J Kalemba

Michael John Rieschi

Gregory Heimann

Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.

Updating compiled native instruction paths

Defining an instruction path to be compiled by a just-in-time (JIT) compiler

Implementing a jump instruction in a dynamic translator that uses instruction code translation and just-in-time compilation

A method for executing non-native instructions in a computing system having a processor configured to execute native instructions may include fetching a first non-native instruction from a plurality of non-native instructions; interpreting the first non-native instruction to generate a first instruction code; compiling the first instruction code to generate a first native instruction corresponding to the first non-native instruction; determining whether to execute the first instruction code or the generated first native instruction; and implementing a first virtual machine instruction corresponding to the first non-native instruction based, at least in part, on determining whether to execute the first instruction code or the first native instruction.

Just-in-time dynamic translation for translation, compilation, and execution of non-native instructions

Dynamic on/off just-in-time compilation in a dynamic translator using instruction code translation

The disclosure relates generally to managing assignment of tasks among instruction processors (IPs) within a computer system having multiple IPs, and more particularly to binding emulated IPs with a host system's IPs (e.g., processor cores) for facilitating control over affinity-based assignment of tasks among the host system's IPs by a task manager (e.g., OS) that is executing on the emulated IPs, rather than running directly on the host system's IPs. Certain embodiments provide techniques for binding emulated IPs with actual IPs of a computing system that is hosting the emulated IPs, thereby enabling better control of management of the system by a task manager executing on the emulated IPs. For instance, in certain embodiments, a dispatcher (e.g., of an OS running on emulated IPs) performs affinity-based management of task assignment for tasks performed for an application program among IPs of a host system that is hosting the emulated IPs.

System and method for affinity dispatching for task management in an emulated multiprocessor environment

An emulation system, computer program product, and method for emulating the execution of a target program comprising instructions of an instruction set of a target computer on a host computer having a different instruction set operate by performing a static translation of the instructions of the target program into a series of instructions of an intermediate instruction set, the intermediate instruction set being optimized for interpretation on the host computer, and then executing the series of instructions of the intermediate instruction set by interpretation on the host computer.

System, computer program product, and methods for emulation of computer programs

A method, a translator, and a computer-readable medium for translating compiled programming code from a first code state to a second code state are disclosed. The programming code in the first state has a plurality of basic blocks, where each basic block has a set of instructions. At least one basic block ends in a dynamic branch, the dynamic branch being a transfer to one of a set of destinations based on a calculation of a destination address. The plurality of basic blocks in the first state of the programming code are identified, as are links between the identified basic blocks. A control flow graph (CFG) of the programming code is then constructed based on the identified basic blocks and identified links, where the CFG is in a preliminary form. At least one basic block ending in a dynamic branch is identified, and all identified basic blocks that lead to the dynamic branch are explored, based on the CFG, as far back as is necessary to fully determine a set of destination addresses for the dynamic branch. The set of destination addresses defines the set of destinations from the dynamic branch. Such set of destinations is examined to identify a branch table, and the CFG is updated to reflect the set of destinations and the identified branch table. The programming code is then translated from the first state to the second state based at least in part on the updated CFG.

Determining destinations of a dynamic branch

An emulation system functions to translate instructions comprising a target application of a target system into corresponding instructions native to a host system and executes the instructions on the host system. During execution, the emulation system encounters target disk read/write operations. As the memory architectures of the host and target computer systems differ, the data in host memory is conformed to a target memory format when data in keyboard memory buffer is processed. Also, the host and target disk controllers cause storage of data on diskettes in differing byte orders. However, the emulation system performs disk/read write operations without byte-reversal prior to disk-write or subsequent to disk read operations. Thus, the host does not produce storage media having data conforming to that of target storage media. However, despite this drawback, the emulation system strikes a favorable balance between the need for precise replication of target application functionality on the one hand, and the importance of overall emulation system performance on the other.

Method for enhanced I/O in an emulated computing environment

A first dynamic link library (DLL) of a first computing environment, which exports one or more procedures that an application program executing in the first computing environment can call, is replaced with a second DLL that executes in a second computing environment, in a manner that is transparent to the calling application. A source code skeleton of the second DLL is automatically generated based on information contained in a directory of the compiled object code of the first DLL. The exported procedures of the second DLL have interfaces that are identical (from the perspective of the calling application) to the interfaces of the corresponding exported procedures of the first DLL, but the exported procedures of the second DLL comprise native code of the second computing environment. The calling application executing in the first computing environment is the linked dynamically to the exported procedures of the second DLL in the second computing environment in a manner that is transparent to the calling application.

METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR REPLACING A DYNAMIC LINK LIBRARY (DLL) OF A FIRST COMPUTING ENVIRONMENT WITH A DLL OF A SECOND COMPUTING ENVIRONMENT THAT CAN BE INVOKED FROM THE FIRST COMPUTING ENVIRONMENT IN A TRANSPARENT MANNER

A method for communicating active messages among nodes of a parallel processing computer system is disclosed. The active messages are defined by .mu.threads, and the method comprises the steps of: (a) generating a .mu.thread comprising an instruction pointer, frame pointer, and Local Parameters pointer from a first node to a second node; and (b) performing a procedure on a data structure in accordance with the .mu.thread. The instruction pointer points to an application specific procedure in system memory, and the frame pointer points to an application specific data structure in system memory. The Local Parameters pointer points to one or more words of additional data or parameters stored in memory mapped device registers or system memory.

Methods and apparatus for exchanging active messages in a parallel

A block structured data processing system concatenates block structured code so as to expedite the execution of less structured language code. The concatenation is performed in a code unit for a parallel pipeline processor so that the concatenated code can be executed in parallel. To optimize the access to the data associated with address couples, an address couple associative memory (ACAM) is provided for the translation of conventional address couples found in block structured systems into general registers numbers. The mechanism attempts to keep data in the general registers thus removing the requirement to re-fetch it from the memory system. To expedite the fetching of data arrays, descriptors may be stored in ACAM for use in continuously accessing data arrays in memory.

Method and means for concatenating multiple instructions

A computer system executes steps to provide results in an order different from an intended order. Instructions are concatenated into a plurality of jobs. Different invocations of a variable within the computer instruction stream may be assigned respectively different storage locations and each storage location may correspond to a different job. When all the storage locations associated with a particular job indicate available resources (e.g. valid variable input), the job may be executed. A mechanism allows for job re-execution, if needed, due to interrupt or error.

Out of order job processing method and apparatus

A memory system provides a method for error detection and correction. Large data words are divided into multiple error correction zones. One zone from each of two or more words are combined to form an error domain. Address bits are also included in the domains. Check bits are generated from the data bits in each domain and stored with the data. During data retrieval, each domain is processed separately, generating a syndrome for each domain. The syndromes provide indication of bit errors, allowing the correction of a single-bit error in each domain. Multiple-bit errors may thus be corrected within each word using a single-bit error correction code. Data are distributed in physical memory so that, within each domain, no more than one data bit is stored in the same memory device. This method provides full error correction capability in the presence of a catastrophic memory package failure, so long as failures in multiple packages do not cause multiple errors within a single error correction domain. During both read and write operations, error correction code processing may be performed in parallel for multiple domains, enhancing performance.

Method and apparatus for effecting multiple error correction in a

An array of various types of processors for the purpose of simulating computer functions for large computer systems. These functions may vary from simple AND, OR and other functions to large arithmetic logic units and even random access memories. The simulation array is a tree-type array where the leaves of the tree are the actual logic simulation processors with the other processors serving as nodes which route change of value notices among the various logic simulation processors.

Growing community of inventors

Minnetonka, MN, United States of America

Andrew T Jennings