Texas Instruments Corporation

Andrew T Appel

Michael F Chisholm

Mahalingam Nandakumar

Howard L Tigelaar

Frank Scott Johnson

Richard A Chapman

Greg Charles Baldwin

Bert R Riemenschneider

A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end with a metal layer, but design rule spacing is still maintained between the connections with the metal layer. The overlapping areas between the rectangular contact and the metal layers are asymmetrical. Alternatively, these overlapping areas are smaller than the design rule overlap requirements. In a second embodiment, a fuse element is constructed with a plurality of rectangular-shaped contacts. As a result, a current value that is significantly lower than conventional fuse current values, can be used to melt such a contact or blow the fuse.

Rectangular contact used as a low voltage fuse element

Capacitance for MIM capacitors is increased by connecting another interdigitated pattern at the poly level in parallel with overlying patterns at the metal levels. The poly layout is optimized to maximize intralevel capacitive coupling through sidewall nitride.

Additional capacitance for MIM capacitors with no additional processing

A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe pads (52) in an H configuration for accurate linewidth measurements. A second test structure (70) may be used alone or in conjunction with the first test structure. A single gate line (72) crosses a moat region (74) several times. This allows both capacitance and gate gate-resistance measurements with the same test structure and for more accurate TLD measurement.

Combination test structures for in-situ measurements during fabrication

A method of fabricating a bipolar transistor concurrently with an MOS device comprising the steps of forming an NPN bipolar transistor by providing a semiconductor wafer (1) having a semiconductor region (3) of predetermined conductivity type having a surface. An emitter region (33) and a collector contact region (35) are formed in and extend to the surface of the semiconductor region (3) of predetermined conductivity type with an implant of the predetermined conductivity type. An intrinsic base region (43) is formed extending to the surface by implanting an impurity of opposite conductivity type in the semiconductor region (3) isolating the emitter region (33) from the semiconductor region of predetermined conductivity type. An insulating layer (49) is formed on the semiconductor region of predetermined conductivity type extending over all transitions at the surface of the predetermined conductivity type to the opposite conductivity type. A portion of the intrinsic base region (43) is then converted to an extrinsic base region (43). A portion of the collector contact (35), a portion of the emitter region (33) and a portion of the extrinsic base region (43) extend to the surface and an electrically conductive silicide (61) is formed at the surface on each of the collector contact (35), emitter region (33) and extrinsic base region (43). A CMOS device is formed in the wafer (1) concurrently with the fabrication of the bipolar transistor.

Vertical NPN transistor for 0.35 micrometer node CMOS logic technology

An apparatus integrating pad conditioning device (44) with a wafer carrier device (24) for chemical-mechanical polishing applications includes an attaching mechanism (45) for associating conditioning device (44) with wafer carrier device (24). Conditioning surface (84) of conditioning device (44) conditions the polishing pad associates with attaching mechanism (45). Carrier device (24) receives and holds wafer (42) so that wafer (42) and conditioning surface (44) contact the polishing pad (42) to simultaneously condition polishing pad (26) and polish wafer (42).

Apparatus integrating pad conditioner with a wafer carrier for

A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During wafer polishing particles build up on the polishing pad (114) reducing its effectiveness. Either during or in between wafer polishing (or both), conditioning head (122) is applied to pad (114) to remove the particles from pad (114) into the slurry (120). Conditioning head (122) comprises a semiconductor substrate (126) that is patterned and etched to form a plurality of geometries (128) having a feature size on the order of polishing pad (114) cell size.

Application of semiconductor IC fabrication techniques to the

A method of forming a CMOS transistor which comprises providing a partially fabricated CMOS structure having a p-type region wherein NMOS devices will be fabricated and an n-type region wherein PMOS devices will be fabricated, a separate pattern defining each region, a thin gate oxide layer in each window and a thin polysilicon gate layer having a thickness up to 3200 .ANG. over the thin gate oxide layer having a thickness up to 90 .ANG.. A layer of glass having a boron doping species therein, preferably borosilicate glass, is deposited over the polysilicon gate layer disposed over the the n-type region. The portion of the polysilicon gate layer disposed defining the p-type region is then doped n-type, preferably by implanting phosphorus, and the structure is heated to cause boron to diffuse from the layer of glass into the polysilicon gate layer over the n-type region. The layer of glass of glass is removed and fabrication of the CMOS device is then completed in standard manner.

Thin polysilicon doping by diffusion from a doped silicon dioxide film

A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During wafer polishing particles build up on the polishing pad (114) reducing its effectiveness. Either during or in between wafer polishing (or both), conditioning head (122) is applied to pad (114) to remove the particles from pad (114) into the slurry (120). Conditioning head (122) comprises a semiconductor substrate (126) that is patterned and etched to fore a plurality of geometries (128) having a feature size on the order of polishing pad (114) cell size.

One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a desired thickness for a gate oxide for the low-voltage device; selectively forming a gate structure (30) for the high-voltage device, the thin oxide is situated between the gate structure and the substrate; and selectively thickening the thin oxide under the gate structure while keeping the thin oxide layer utilized for the low-voltage device at the desired thickness.

Process for thickening selective gate oxide regions

Semiconductor substrate conditioning head having a plurality of

A compact system and method for chemical-mechanical polishing. A polishing pad (114) is attached to a non-rotating platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. Energy (e.g. ultrasonic) is coupled from device (122) to the platen (112). Energy is thus applied to the pad/wafer interface to aid in the removal of surface material from wafer (116) and for pad conditioning. New slurry is added to wash the particles off the edges of the pad (114).

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Dallas, TX, United States of America

Andrew T Appel