Agilent Technologies, Inc.

Verigy (Singapore) Pte. Ltd.

Verigy Ipco

Advantest (Singapore) Pte Ltd

Verigy Pte. Ltd.

Andrew Steven Hildebrant

Reid F Hayhow

Domenico Chindamo

David Dowding

Methods and systems for estimating cost for device testing are disclosed. In one embodiment, the method comprises reading a test file having a plurality of test vectors, determining a required memory needed to execute the plurality of test vectors, and using the required memory to estimate a cost to execute the test vectors.

Cost estimation for device testing

A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein, and applying the test patterns with timing irregularities injected therein to input receivers of the DUT. A tester is configured to test loopback functionality of a device under test (DUT) utilizing a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT.

Source synchronous timing extraction, cyclization and sampling

Systems and methods for adaptively compressing test data are disclosed. One such method comprises the steps of examining a test data file that includes a first plurality of data units corresponding to a first plurality of DUT pins and a second plurality of data units corresponding to a second plurality of DUT pins, compressing the first plurality of data units using a first compression technique, and compressing the second plurality of data units using a second compression technique.

Systems and methods for adaptively compressing test data

A wireless integrated circuit test method and system is presented. The invention allows testing of one or more integrated circuits configured with a wireless interface and a test access mechanism which controls input of test data received over a wireless connection from a test station to test structures which test functional blocks on the integrated circuit. Via the wireless connection, multiple integrated circuits or similarly equipped devices under test can be tested simultaneously. The invention also enables concurrent testing of independently testable functional blocks on any given integrated circuit under test.

Wireless no-touch testing of integrated circuits

A method for testing a device-under-test (DUT) includes examining a test data file that includes test data for testing the structure, functionality and/or performance of the DUT. The method also includes separating a first plurality of data units from a second plurality of data units contained in the test data file. The first plurality of data units correspond to a first plurality of DUT pins, and the second plurality of data units correspond to a second plurality of DUT pins.

Systems and methods for testing a device-under-test

A method and apparatus for verifying an integrated circuit device test for testing an integrated circuit device on an automated tester is presented. An integrated circuit device simulator simulates a flawed integrated circuit device that models one or more known flaws, or physical defects, in an assumed good integrated circuit device design. A tester simulator simulates the integrated circuit device test which sends stimuli to, and receives responses from, the simulated flawed integrated circuit device. A test analyzer then determines whether the simulated test of the simulated flawed integrated circuit device detected the flaws in the simulated flawed integrated circuit device and properly failed the simulated flawed integrated circuit device.

Verification of integrated circuit tests using test simulation and integrated circuit simulation with simulated failure

A translator tool for translating simulation test data generated to test clock recovery circuitry of a device from an event-based format to a cycle-based format readable by integrated circuit testers is presented. The simulation test data includes test timing irregularities intentionally injected into a serial data signal that will be processed by the clock recovery circuitry of the device under test. The translator tool includes a normalization function that extracts the intentionally injected timing irregularities from the event-based test data and generates corresponding normalized event-based test data without the extracted timing irregularities. The translator tool includes a cyclization engine that cyclizes the normalized event-based test data to generate corresponding cycle-based test data without the timing irregularities. Preferably, the extracted timing irregularities are stored and formatted into a timing irregularities file readable by the integrated circuit tester to allow the tester to reinject the timing irregularities back into the cycle-based test data using its own timing irregularities injection tools.

A method for testing performance of a device-under-test (DUT) includes: examining vectors, each of the vectors including a plurality of characters; and creating waveform entries, each of the waveform entries corresponding to a distinct vector configuration encountered among the vectors examined.

Systems and methods for testing performance of an electronic device

A list of waveforms is received (the list being one that is to be driven to or received from a pin of a device under test). The list of waveforms is de-interleaved to form lists of non-interleaved waveforms. Each list of non-interleaved waveforms is then optimized by combining at least two of its entries. By way of example, the above method may be implemented by program code stored on a number of computer readable media, or by a circuit tester having program code for implementing same.

Methods and apparatus for optimizing lists of waveforms

A list of waveforms is received (the list being one that is to be driven to or received from a pin of a device under test, and each waveform in the list being associated with a weight). For each of at least two waveforms in the list, a number of test sample points lost by masking the waveform with a particular parent waveform in a child-parent waveform map is calculated. The number of lost test sample points is determined by 1) a difference in the number of test sample points in the waveform and the number of test sample points in the particular parent waveform, and 2) the weight associated with the waveform. In response to the calculations, a waveform masking is implemented such that the implemented waveform masking results in fewer lost test sample points than another waveform masking.

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Loveland, CO, United States of America

Andrew Steven Hildebrant