Xmos Limited

Andrew Stanford-Jason

Hendrik Lambertus Muller

Daniel John Pelham Wilkinson

Michael David May

Nigel Jürgen Toon

Sam Chesney

A system comprising a microphone arranged to capture sound from an environment, and an ultrasound emitter configured to emit an emitted ultrasound signal into an environment. The microphone is arranged to capture a received audio signal from the environment, comprising a component in the human audible range. The microphone is also arranged to capture a received ultrasound signal comprising reflections of the emitted ultrasound signal, or else the system comprises another, co-located microphone arranged to capture the received ultrasound signal. Either way, the system further comprises a controller implemented in software or hardware or a combination thereof, wherein the controller is configured to process the received audio signal in dependence on the received ultrasound signal.

Capturing and processing sound signals for voice recognition and noise/echo cancelling

A method of using a directional microphone unit having an array of constituent microphones. Each of a plurality of the microphones receives substantially white noise via a direct path from a source, and also receives an echo comprising a reflection of the white noise from at least one surface, thereby obtaining a received noise signal comprising a combination of the directly-received noise and the echo. For each of the plurality of microphones, a spacing is identified between lobes and/or troughs in a respective spectrum of the received noise signal as received by the respective microphone, thereby determining an additional distance travelled by the echo to the respective microphone relative to the direct path. A direction of the source is calculated based on the additional distance travelled for each of said plurality of microphones.

Processing echoes received at a directional microphone unit

A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.

Interface between a bus and a inter-thread interconnect

A method and corresponding tool, the method comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by matching a plurality of the lower-level nodes and edges to higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more lower-level nodes and one or more associated edges; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor. The higher-level structure nodes are selected exclusively from a predetermined set of structure node patterns, each pattern in the set having at most one entry point and at most one exit point.

Structural analyser

A method and corresponding tool for estimating program execution time. A higher-level structure is received as an input, representing control flow through an executable program. The higher-level structure comprises one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes. The levels of the higher-level structure are probed to extract a substructure representing a route through the program from a start instruction to an end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes. An execution time for the route through the program is estimated based on the extracted substructure, and a modification affecting the execution time is made in dependence on the estimation.

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Salisbury, United Kingdom

Andrew Stanford-Jason