Hughes Aircraft Company

Yang, Chao K.

Rosman, Andrew

Ellis, Thomas O.

Moise, Norton L.

Mcmillen, Robert J.

Landis, Gary N.

Nack, Myron L.

Yang, Chao

Andrew Rosman

Thomas O Ellis

Robert J McMillen

Gary N Landis

Myron L Nack

Robert J Mcmillen

Norton L Moise

Chao Yang

Chao K Yang

A system using a ray-tracing algorithm and a hierarchy of volume elements (called voxels) to process only the visible surfaces in a field of view. In this arrangement, a dense, three-dimensional voxel data base is developed from the objects, their shadows and other features recorded, for example, in two-dimensional aerial photography. The rays are grouped into subimages and the subimages are executed as parallel tasks on a multiple instruction stream and multiple data stream computer (MIMD). The use of a three-dimensional voxel data base formed by combining three-dimensional digital terrain elevation data with two-dimensional plan view and oblique view aerial photography permits the development of a realistic and cost-effective data base. Hidden surfaces are not processed. By processing only visible surfaces, displays can now be produced depicting the nap-of-the-earth as seen in low flight of aircraft or as viewed from ground vehicles. The approach employed here is a highly-parallel data processing system solution to the nap-of-the-earth flight simulation through a high level of detail data base. The components of the system are the display algorithm and data structure, the software which implements the algorithm and data structure and creates the data base, and the hardware which executes the software. The algorithm processes only visible surfaces so that the occulting overload management problem is eliminated at the design level. The algorithm decomposes the image into subimages and processes the subimages independently.

Digital visual and sensor simulation system for generating realistic

A computer which achieves highly parallel execution of programs in instruction flow form, as distinguished from data flow form employing a unique computer architecture in which the individual units such as, process control units, programmable function units, memory units, etc., are individually coupled together by an interconnection network as self-contained units, logically equidistant from one another in the network, to be shared by any and all resources of the computer. All communications among the units now take place on the network. The result is a highly parallel and pipelined computer capable of executing instructions or operations at or approaching full clock rates. Each process control unit initiates its assigned processes in sequence, routing the first instruction packet of each process through the network and addressed memories and function units back to the initiating process control unit where it is relinked with its process. As each instruction packet is routed, the initiating process is suspended until relinking occurs. Because the instruction flow computer is fully pipelined, the first instruction packet of the second process follows on the next machine cycle, and so on, until all of the processes have been initiated, providing time sharing of a single pipeline by multiple instruction packet streams.

MIMD instruction flow computer architecture

A packet switching node which processes applied data packets containing routing tag signals indicative of the output port destination to which the data packets are to be applied. The invention comprises an N.times.M switch node that accepts data packets at any of N input ports and routes each to any of M output ports. The output selected is determined by the routing tag signal in the packet. The node comprises a multiport memory having a predetermined number of memory locations available for storage of data packets applied to each of a plurality of input ports. Control logic coupled to the input and output ports and memory is designed so that the data packets are effectively sorted according to their desired output port destination. The control logic comprises arbitration logic which randomly, in a statistical sense, chooses among any data packets that are directed to the same output port. The algorithm implemented by the arbitration logic is designed so that data packets will not wait indefinitely to be routed from the switch node. A method in accordance with the present invention comprises sorting and storing the data packets based upon the output port destination and then arbitrating among the data packets. The final step involves routing the data packets selected during the arbitration processes to the output ports identified in the routing tag signals.

Packet switched multiport memory NXM switch node and processing method

Growing community of inventors

Los Alamitos, CA, United States of America

Andrew Rosman