Nvidia Corporation

Andrew Robert Kerr

John Tran

Stuart F Oberman

Jack H Choquette

Ming Yiu Siu

Jeffrey Michael Pool

Alan Kaatz

Shirish C Gadre

Steven James Heinrich

Olivier Giroux

Xiaogang Qiu

Manan Patel

Omkar Paranjape

Poornachandra Rao

Vinod Grover

Sean Jeffrey Treichler

Ronny Krashinsky

Sean Jong Lee

Girish Bharambe

Kyrylo Perelygin

Scott Ricketts

Apoorv Parle

Harold Carter Edwards

Maciej Piotr Tyrlik

Konstantinos Kyriakopoulos

Igor Sevastiyanov

Rishkul Kulkarni

Mostafa Hagog

Julien Demouth

Gokul Ramaswamy Hirisave Chandra Shekhara

Edward H Gornish

Aditya Avinash Atluri

Michael Andersch

Balaji Krishna Yugandhar Atukuri

Mike Murphy

Bageshri Sathe

David Allan Berson

Haicheng Wu

Vijay Thakkar

Cody Addison

Aman Arora

James Player

Cris Cecka

Matthew Grant Bolitho

Apparatuses, systems, and techniques are presented to compile code. In at least one embodiment, one or more compilers are to compile one or more compiled portions of code with one or more intermediate representations of one or more portions of code.

Kernel fusion for machine learning

A method, computer readable medium, and processor are described herein for inline data inspection by using a decoder to decode a load instruction, including a signal to cause a circuit in a processor to indicate whether data loaded by a load instruction exceeds a threshold value. Moreover, an indication of whether data loaded by a load instruction exceeds a threshold value may be stored.

Inline data inspection for workload simplification

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Application programming interface to wait on matrix multiply-accumulate

A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

Techniques for efficiently transferring data to a processor

A method, computer readable medium, and system are disclosed for inline data inspection. The method includes the steps of receiving, by a load/store unit, a load instruction and obtaining, by an inspection circuit that is coupled to the load/store unit, data specified by the load instruction. Additional steps include determining that the data equals zero and transmitting the data and a predicate signal to the load/store unit, wherein the predicate signal indicates that the data equals zero. Alternative additional steps include computing a predicate value based on a comparison between the data and a threshold value and transmitting the data and the predicate value to the load/store unit, wherein the predicate value is asserted when the data is less than the threshold value and is negated when the data is not less than the threshold value.

One embodiment of the present invention includes a dependency extractor and a dependency investigator that, together, facilitate performance analysis of computer systems. In operation, the dependency extractor instruments a software application to generate run-time execution data for each work task. This execution data includes per-task performance data and dependency data reflecting linkages between tasks. After the instrumented software application finishes executing, the dependency investigator evaluates the captured execution data and identifies the critical path of tasks that establishes the overall run-time of the software application. Advantageously, since the execution data includes both task-level performance data and dependencies between tasks, the dependency investigator enables the developer to effectively optimize software and hardware in computer systems that are capable of concurrently executing tasks. By contrast, conventional performance analysis may not correctly identify critical paths in software applications that execute tasks in parallel across multiple processing units and, consequently, may misdirect optimization efforts.

Determining overall performance characteristics of a concurrent software application

A technique is disclosed for executing a compiled parallel application on a general purpose processor. The compiled parallel application comprises parallel thread execution code, which includes single-instruction multiple-data (SIMD) constructs, as well as references to intrinsic functions conventionally available in a graphics processing unit. The parallel thread execution code is transformed into an intermediate representation, which includes vector instruction constructs. The SIMD constructs are mapped to vector instructions available within the intermediate representation. Intrinsic functions are mapped to corresponding emulated runtime implementations. The technique advantageously enables parallel applications compiled for execution on a graphics processing unit to be executed on a general purpose central processing unit configured to support vector instructions.

Method for compiling a parallel thread execution program for general execution

Growing community of inventors

Atlanta, GA, United States of America

Andrew Robert Kerr