United States Of America As Represented By The Secretary Of The Air Force

Nammo Talley, Inc.

USA As Represented By Secretary Of The Navy

Andrew Richard Davis

Kenneth Vaccaro

Joseph P Lorenzo

Eric A Martin

Helen M Dauplaise

Eric Scheid

Gregory D Knowlton

Thomas M Deppert

Mark A Skidmore

Joshua E Gwaltney

Thomas V Palen

William E McNicholas

Christian W Salafia

Matt E Cummings

Wayne R Mayville

Stephen M Spaziani

Robert S Willhelm

Chad Lewis Greenlee

John Johnson

Glade Hansen

Provided is a frangible munitions device optimized for a dome and cylinder that yields fragments having shapes corresponding to a predetermined embossment pattern upon explosive rupture. The embossment pattern includes a first set of inner regular hexagonal embossments formed into the dome and cylinder that are aligned with the axis of the cylinder, and a second set of outer pre-deformed hexagonal shapes that distort to produce regular hexagonal shapes after drawing into the cylinder wall. The second set of shapes are separated by sharp transition regions. The shapes are embossed in a repeated pattern around the hollow cylinder and the dome top. The dome yields a plurality of fragments having shapes corresponding to the first set of inner regular hexagonal embossments upon explosive rupture, while the cylinder yields a plurality of fragments having shapes corresponding to the second set of outer pre-deformed hexagonal embossments upon explosive rupture.

Fragmentation pattern, optimized for drawn cup warheads with a dome and cylindrical wall

The invention provides a short-range, self-propelled, non-fragmenting breaching device to breach a wide variety of doors and barricades with high efficiency, high gunner safety and low collateral damage. The invention also provides a method of preparing the breaching device and a method of breaching a target using the breaching device.

40mm door-breaching grenade

The invention provides a method and a system for defeating a target containing a flammable or explosive fill and an incendiary penetrating projectile for use in the method and the system. The incendiary penetrating projectile contains a non-detonating incendiary composition that is ignited prior to penetrating a target.

Mine defeat system and pyrotechnic dart for same

An aqueous thiourea-ammonia treatment is used to form a thin sulfurous film at the indium phosphide surface, having a thickness of less than one nanometer. The thiourea-ammonium hydroxide treatment can be used as is or immediately prior to deposition of cadmium sulfide for enhanced surface passivation. The thiourea-ammonium hydroxide treatment is entirely compatible with chemical bath deposition, molecular beam epitaxy, or metalorganic chemical vapor deposition of the cadmium sulfide.

Method for obtaining a sulfur-passivated semiconductor surface

A novel indium phosphide (InP) based heterojunction bipolar transistor (HBT) is described. A II-VI compound, cadmium sulfide (CdS), is used as the emitter to improve the emitter injection efficiency and reduce recombination losses. The cadmium sulfide emitter is applied following the epitaxial growth of III-V compound collector and base regions. The large valence band discontinuity (.quadrature.E=0.75 eV) between CdS and InP allows InP to be used for both the base and collector material. Prior to cadmium sulfide deposition, the exposed surfaces of the epitaxial layers can be passivated with sulfur, further reducing the recombination losses.

Cadmium sulfide layers for indium phosphide-based heterojunction bipolar

In a Schottky metal junction semiconductor device, a CdS interface layer, having a thickness of under 100 angstroms, is positioned under the Schottky barrier gate of a III-V HEMT, for reducing gate leakage, and for enabling full depletion of the conducting channel. A similar layer is positioned under the insulator of an MIS device having an InP substrate. The CdS layers are deposited from a chemical bath which merely entails a simple, safe and readily controllable additional step in the otherwise conventional manufacturing process of these devices.

Cadmium sulfide interface layers for improving III-V semiconductor

An InP buffer layer is first formed upon an InP substrate; a thin layer of heavily doped InGaAs, a thick layer of light absorbing InGaAs, and a thin layer of InAlAs are thereafter sequentially grown upon the InP buffer layer. A light reflective Schottky barrier metallic layer is then applied to the InAlAs layer and the resulting device is inverted and affixed to a newly provided substrate, to thus shield and protect the sensitive Schottky contact. The InP substrate layers are thereafter removed and the now exposed thin, heavily doped InGaAs layer is coated with a transparent, electrically conductive layer of Indium-tin-oxide.

Transparent ohmic contacts for Schottky diode optical detectors on thin

A full wafer to full wafer integrated circuit apparatus wherein substrate removal and replacement on one wafer has been used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo feed effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.

Wafer joined optoelectronic integrated circuits

A full wafer to full wafer integrated circuit fabrication process wherein substrate removal and replacement of one wafer is used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo field effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.

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Mesa, AZ, United States of America

Andrew Richard Davis