Advanced Micro Devices Corporation

Globalfoundries Inc.

Andrew R Rawson

Geoffrey S Strongin

Garth D Hillman

Ralf Findeisen

Gary H Simpson

In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the processor has been defined, wherein the processor does not implement the modification. The circuitry is configured to detect the instruction or its memory operands and cause a transition to Known Good Code (KGC), wherein the KGC is protected from unauthorized modification and is provided from an authenticated entity. The KGC comprises code that, when executed, emulates the modification. In another embodiment, an integrated circuit comprises at least one processor core; at least one other circuit; and a KGC source configured to supply KGC to the processor core for execution. The KGC comprises interface code for the other circuit whereby an application executing on the processor core interfaces to the other circuit through the KGC.

Known good code for on-chip device management

A system including a first module and a second module. The first module includes a linear feedback shift register (LFSR) and a permutator circuit. The LFSR outputs a pseudo-random sequence of digital values based on a stored key value. The permutator circuit operates on successive groups of input bits using the pseudo-random sequence. For each of said successive groups, the permutator circuit: (a) selects a bit permutation based on a respective one of the digital values in the pseudo-random sequence, (b) permutes the bits of the group using the selected bit permutation to obtain a resultant group of bits, and (c) transmits the resultant group onto an output bus. The second module also includes an LFSR and a permutator circuit that operate to invert the permutations applied by the first module. In a two-dimensional embodiment, the first module and second module may include additional circuitry for scrambling bits between groups.

Hardware based multi-dimensional encryption

Uses of known good code for implementing processor architectural modifications

Growing community of inventors

Austin, TX, United States of America

Andrew R Rawson