International Business Machines Corporation

Andrew R Ranck

Clinton E Bubb

Thomas D Needham

Pritish Ranjan Parida

Silvio Dragone

Vincenzo Condorelli

Jie Zheng

Nihad Hadzic

Mushfiq U Saleheen

William Santiago Fernandez

Avery W Hagleitner

Elisabeth Andreassen

Robert Brett Tremaine

Mark Anthony Check

A system and method and computer program product for cognitive recording and sharing of live events. The system includes: a sensing and transmitting device that can sense the biometric signatures of an individual; a processing unit that analyses the sensed signal and initiate a set of actions; a recording device or the like to record the event; and a networked sharing device configured to subsequently share recorded event content. The system further identifies individuals' pre-cognitive inputs and additional external and internal factor input signals that are precursors to cognitive affirmation of an emotional response. These inputs will be identified, correlated, and used in training the system for subsequent identification and correlation between input factors and resulting emotional state. External factors may include: recognized emotional states, biometric inputs, and/or precognition inputs of other individuals in proximity to the subject individual. Other factors may include an individual's context.

Cognitive recording and sharing

Communication between one communication bus having one set of characteristics and another communication bus having another set of characteristics is facilitated by a bridge coupling the two communication buses. The bridge includes a scoreboard to manage data communicated between the buses. In one particular example, the one communication bus is a Processor Local Bus (PLB6) and the other communication bus is an Application Specific Integrated Chip (ASIC) Interconnect Bus (AIB).

Bridging between differing communication buses

A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.

Access and protection of I2C interfaces

Embodiments relate to modular reductions. An aspect includes a system to perform modular reductions. The system includes a shift register to store an input string or number. The system also includes a plurality of processing elements arranged in a pipeline configuration to convert the input string to a predefined alphabet or to convert the number to a different base based on a plurality of modular reductions, an output of one of the plurality of processing elements being an input to a subsequent one of the plurality of processing elements in the pipeline as part of a recursive division, and an input of a first one of the plurality of processing elements in the pipeline being an output of the shift register.

Pipelined modular reduction and division

An embodiment includes an integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD. The IC includes an input/output (I/O) interface and a PLD interface. The I/O interface converts a signal format between the IC and the PLD. The PLD interface includes a configuration and status register, a data buffer, and pacing logic. The configuration and status register is adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface. The data buffer temporarily holds PLD programming data received from a DMA control at a DMA speed. The pacing logic controls the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.

Using direct memory access to initialize a programmable logic device

An embodiment includes using direct memory access (DMA) to initialize a programmable logic device (PLD). An aspect of the invention includes manipulating a control line of the PLD to configure the PLD in a programming mode. PLD programming data is received at a PLD interface from a DMA control at a DMA speed. The PLD interface controls access of a processor and the DMA control to a programming port on the PLD. The PLD interface includes a data buffer and pacing logic. The PLD programming data is written to the data buffer and read from the data buffer. The PLD programming data transmitted to the programming port on the PLD at a PLD programming speed. The pacing logic of the PLD interface controls the data transmission at the PLD programming speed, and the DMA control is configured to transform the PLD programming data while the processor performs other processing tasks.

A system to determine fault tolerance in an integrated circuit may include a programmable logic device carried by the integrated circuit. The system may also include a configurable memory carried by the programmable logic device to control the function and/or connection of a portion of the programmable logic device. The system may further include user logic carried by said programmable logic device and in communication with a user and/or the configurable memory. The user logic may identify corrupted data in the configurable memory based upon changing user requirements.

System to determine fault tolerance in an integrated circuit and associated methods

Methods, systems, and computer program products for using direct memory access (DMA) to initialize a programmable logic device (PLD) are provided. A method includes manipulating a control line of the PLD to configure the PLD in a programming mode, receiving PLD programming data from a DMA control at a DMA speed, and writing the PLD programming data to a data buffer. The method also includes reading the PLD programming data from the data buffer, and transmitting the PLD programming data to a programming port on the PLD at a PLD programming speed.

Growing community of inventors

Poughkeepsie, NY, United States of America

Andrew R Ranck