Synopsys, Inc.

Andrew R Brown

Plamen A Asenov

Salvatore Maria Amoroso

David Thomas Reid

Jaehyun Lee

Manuel Aldegunde Rodriguez

Binjie Cheng

Andrew John Pender

The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

Dynamic random-access memory pass transistors with statistical variations in leakage currents

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Glasgow, United Kingdom

Andrew R Brown