Lsi Logic Corporation

Csr Technology Inc.

Zoran Corporation

Neomagic Corporation

Mitel Semiconductor Limited

Mitel Semiconductor Americas Inc.

Andrew Popplewell

Stephen Williams

Razmik Karabed

Albert S Kuo

Nersi Nazari

Bassel Haddad

Paul C Gregory

Maxim Mogilnitsky

Isaiah A Carew

Cenk Yildiz

A partial HDMI physical layer ('phy') decoder core is used in an audiovisual (A/V) sink device to perform HDCP pre-authentication on inactive HDMI ports, so as to enable fast switching between HDMI ports. Whenever a source device is connected to the any HDMI port of the A/V sink device, HDCP authentication is performed on that port immediately, even if A/V data on that port is not being output to a user. As a result, when the user switches between HDMI channels, the output is available to the user instantly, without any HDCP-related delay. The A/V sink includes the partial HDMI phy decoder core in addition to a full HDMI phy decoder core. The full HDMI phy decoder core is used to extract and decode signals received on the active port. The partial HDMI phy decoder core is used to extract and decode only those HDMI signals received on an inactive port that are needed for pre-authenticating the inactive port.

Fast port switching in an audiovisual receiver by use of port pre-authentication by a partial PHY decoder core

A method and apparatus are provided for serial advanced technology attachment (SATA) hot unplug. In one embodiment, a method includes detecting a connection of a SATA storage device to a SATA host interface by monitoring physical (PHY) layer signals derived from SATA communication terminals, by a controller of the host interface. The detection being based on phase locked loop (PLL) response of the PHY layer signals. The method further includes detecting disconnection of the SATA device based on the PLL response and outputting a notification, by the controller, when the PLL response indicates that the SATA device has been disconnected.

Method and apparatus for SATA hot unplug

A method and apparatus for calibrating the slice level of a pulse detector monitors the quality of the detected pulse signal to determine and optimize slice level. The method practiced may include two parts, including a coarse stage and a fine stage. The method practiced may further include a continuous adjustment mode of operation.

Method and apparatus for optimization of data pulse detection slice level

An on-chip data independent method and apparatus for channel error estimation in a data recovery scheme is based on measuring phase noise statistics. The apparatus () receives a data pulse and four quadrature clock signals and has a discriminating device () to provide a count signal for each data pulse received depending on which clock signal was the first to clock the particular data pulse. A pair of counters (and) counts the number of data pulses received at different phase offsets to provide a value representing a statistical ratio of the counts at different clock phase offsets from which an error rate for the received data pulses based on the counts at different clock phase offsets can be determined from a look-up table (). By re-configuring the circuitry, the system can be adapted to measure clock window asymmetry.

Method and apparatus for estimation of error in data recovery schemes

An apparatus generally having a threshold slicer, a state logic device and a converter. The threshold slicer may be configured to generate a (i) first signal having an initial state of a plurality of states in response to a preceding value and a present value from an input signal and (ii) a second signal having a plurality of levels in response to the preceding value and the present value. The state logic device may be configured to generate a third signal having a sequence of the plurality of states starting with the initial state in response to the first signal. The converter may be configured to generate an output signal having the plurality of levels in response to the plurality of states in the third signal.

Data slicers

A phase detector determines a phase error value dependent on the relative phase between a local oscillator signal, used for the system clock, and an input signal received over a PR (a, b, b, a) channel. The error value is used to lock the phase and frequency of an input signal to the phase and frequency of the clock in a phase-lock loop (FIG.,, not shown). The input signal is sampled at regular intervals in accordance with the local oscillator signal, and the sampled values provided on a line,. A threshold slicer,selects an ideal sample value for a sampling point by comparing the sampled values with thresholds received on threshold inputs,to,. A subtracter,determines a difference value which corresponds to a difference between the ideal sample value and the actual sample value for that sampling point. A subtracter,and a delay register,operate to determine the sense of change to the ideal sample value from a ideal sample value for a preceding sampling point. A second subtracter,and a second delay register,determine the sense of change to the ideal sample value for a preceding sampling point from a ideal sample value for a twice preceding sampling point. The phase error value provided is dependent on the senses of change detected and on the difference value.

Phase detector that samples a read signal at sampling points and delay

A phase detector determines an error value dependent on the relative phase between a local oscillator signal, used as the system clock, and an input signal received over a PR (a, b, a) channel. The phase error value is used to control a phase locked loop (FIG. 1, not shown). The received signal is sampled at regular intervals dependent on the local oscillator signal. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled value to three thresholds provided on respective ones of slicer threshold inputs 23, 24 and 25. A subtracter 27 determines a difference value corresponding to a difference between the ideal sample value and the actual sample value for that sampling point. A delay register 28 and a subtracter 29 operate to determine the sense of change to the current ideal sample value from an ideal sample value for a preceding sample point. An output of the subtractor is applied to the switching input of a switch, which thereby provides as an output signal either the difference value or the inverse of the difference value, provided by an inverter 32, dependent on the detected sense of change.

Phase detectors

A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal. The encoder provides a 'systematic' encoding scheme in which for many code strings the encoded bits are the same as the input bits used to generate the encoded bits. This systematic approach of the present invention provides an encoder that is easy to implement because a majority of the bits directly 'feed through' and non-trivial logic circuits are only needed to generate the control bits. The systematic encoding also dictates a decoder that is likewise easy to construct and can be implemented in a circuit that simply discards the control bit. The encoder preferably comprises a serial-to-parallel converter, a code generator, and a parallel-to-serial converter. The code generator produces a rate 16/18 or 16/17 code. The present invention also includes a method that is directed to encoding bit strings and comprises the steps of: 1) converting the input strings to input bits, and 2) adding at least one bit to produce an encoded string with many ones and a Hamming distance greater than one after precoding.

Growing community of inventors

Manchester, United Kingdom

Andrew Popplewell