Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Motorola Corporation

Andrew Paul Hoover

Matthew S Berzins

Brian M Millar

Moon-Su Kim

Naya Ha

David A Petermann

Jong-Ku Kang

Chandrakanth Ramesh

Mark Stephen Rodder

Thomas Michael King

Rwik Sengupta

Charles A Cornell

Milind P Padhye

Robert Harbour

Denise Carol Riemer

Jongyoon Jung

Winford Lee Hill, Ii

Dale John McQuirk

Sam Tower

Gregory Alan Miller

Christopher Alan Peura

A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

System and method of analyzing integrated circuit in consideration of a process variation and a shift

A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.

Power rail for standard cell block

According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.

Power grid and standard cell co-design structure and methods thereof

According to an example embodiment, an integrated circuit may include a plurality of cells and a plurality of paths that supply power to the plurality of cells, respectively. The plurality of cells and the plurality of paths may be arranged based on a plurality of propagation delays of the plurality of cells, which include a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths and a plurality of second delays of the plurality of cells generated based on a plurality of arrival timing windows that overlap each other.

Integrated circuit including cells/gates arranged based on supply voltage variations of cells and influence between cells, and design method thereof

According to one general aspect, a method may include receiving a data file that includes placement data regarding a plurality of circuit cells. The circuit cells may include respective layout portions. The layout portions may be associated with a plurality of respective lithographic colors. The method may include determining if a violating circuit cell is to be re-colored. The method may include indicating that, via at least one shape on a color swap layer in the data file, the violating circuit cell is to be at least partially re-colored. A color swap layer shape may cause a mask generator to re-color the portion of the violating circuit cell indicated by the color swap layer shape.

Method of resolving color conflicts for cell-based designs with multi-pattern lithography

A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

System and method of analyzing integrated circuit in consideration of a process variation

According to one general aspect, a method may include dividing circuit cells into colorable sub-portions, wherein each circuit cell includes one or more colorable sub-portions. The method may include determining if a violating colorable sub-portion is to be re-colored. The method may include indicating that the violating colorable sub-portion is to be at least partially re-colored.

Method of resolving multi-patterned color conflicts for multi-row logic cells

According to one general aspect, a method may include receiving a circuit model that includes logic circuits that are represented by respective cells. The method may include providing a timing adjustment to the circuit model. This providing may include determining one or more respective cells that are candidates for adjustment by employing a sub-micron stress effect, and, for each candidate, replacing a candidate cell with a stressed cell, wherein a candidate cell and stressed cell perform a same logical function. Each stressed cell may include: a gate electrode, a first gate-cut shape disposed to cut the gate electrode, wherein the first gate-cut shape is disposed upon a row-boundary, a second gate-cut shape disposed upon the row-boundary, a gate-cut break disposed between the first gate-cut shape and the second gate-cut shape, an active region, and an active-cut shape disposed to cut the active region.

Using deep sub-micron stress effects and proximity effects to create a high performance standard cell

An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Integrated circuit with a programmable delay and a method thereof

A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an isolation signal. In response to a reference voltage supplied to the latch being restored to a normal operating voltage, indicating that the integrated circuit has transitioned from the low-power mode to a normal mode, a data restoration circuit provides the retained data at the output of the latch prior to negation of the isolation signal. This reduces the likelihood that a delay in negation of the isolation signal will result in the latch output providing incorrect data, thereby reducing the likelihood of the latch output causing errors in downstream elements of the integrated circuit.

Latch device having low-power data retention

A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal.

Circuitry and method for buffering a power mode control signal

A flip-flop () has a normal mode and a low power mode to save power. The flip-flop () has a master latch () and a slave latch (). The slave latch () is used to retain the condition of the flip-flop () during the low power mode, where power is withdrawn from the master latch () but maintained on the slave latch (). The slave latch () may use transistors with lower leakage characteristics than the transistors that make up the master latch (). These lower leakage characteristics may be achieved by a higher threshold voltage and/or a thicker gate dielectric. Operating speed of the flip-flop () is maintained by implementing the slave latch () so that no logic gate or switching transistor is in the critical timing path. Instead, the slave latch () has an input/output terminal to tap into the signal path between the master latch and an output circuit ().

Flip-flop circuit having low power data retention

Methods and architectures for code phase searching spread spectrum signals having a repeating sequence of bits. The signals are searched virtually in parallel by segmenting with a divider ( ) received signals by sequentially, partially correlating signal segments with a corresponding replica signal segments for a predetermined number of phase delays during a time interval not greater than that required to form the next signal segment. Multiplexors ( ) and ( ) provide Doppler and replica signal segments data from Doppler signal and replica signal generators ( ) and ( ) to corresponding multipliers ( ) and ( ), respectively, for multiplication with corresponding signal segments in a segment register ( ). The partial correlation results for each phase delay and at each Doppler frequency are stored in corresponding memory locations in a coherent accumulation RAM ( ). The signals may be searched over one or more phase delays and at one or more Doppler frequencies.

Spread spectrum receiver architectures and methods therefor

A method for forming al buried contact begins by forming an exposed contact area (22) of a substrate (10) having a surface (11). An undoped or lightly doped layer of polysilicon (32) is formed in contact with the contact area (22). A contiguous masking layer (36) is formed over one or more of the contact areas (22) to cover a contact portion of the layer (32) while exposing other portions of the layer (32). The other portions of the layer (32) are doped with dopant atoms (44). A heat cycle is used to laterally drive the dopant atoms (44) through the layer (32) and downward through a substrate surface (11) to form buried contact substrate-diffused regions (54). The resulting regions (54) have improved voltage punch-through resistance to laterally adjacent electrical diffusion regions since the masking layer (36) creates a longer thermal diffusion path for the dopant atoms which eventually reside in the regions (54).

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Austin, TX, United States of America

Andrew Paul Hoover