Integrated Device Technology, Inc.

Andrew P Ng

Philip A Bourekas

A direct mapped cache with cache locking according to one embodiment of the present invention includes a physical address latch and a multiplexing means. The multiplexing means receives the physical address from the physical address latch and exchanges a physical address tag bit with a physical address index bit to generate a cache tag address and a cache index address to divide the cache into two halves, each half servicing a contiguous address range of main memory.

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Mountain View, CA, United States of America

Andrew P Ng