Teranex, Inc.

Martin Marietta Corporation

Andrew P Abercrombie

Woodrow L Meeker

Michele D Van Dyke-Lewis

David A Duncan

Ronald W Schoomaker

Surachai Sutha

Wlodzimierz Holsztynski

Mark S Tomassi

An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array. In another aspect, a programmer references images via pointers to image descriptors that include the actual addresses of various bits of multi-bit data. Other features facilitate and speed up the movement of data into and out of the apparatus. &ldquo;Hit&rdquo; detection and histogram logic are also included.

Mesh connected computed

Mesh connected computer

An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming &ldquo;supercells&rdquo; within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register. These registers have bit values corresponding to respective columns (for the X Pattern register) and rows (for the Y Pattern register) of the array. Patterns can be propagated from these registers into corresponding rows and columns. Further these registers can be used to receive values representing the logical OR of signals generated by individual PEs within respective rows and columns. Further, a number of global data registers are used to store information which can be broadcast back into the processing array.

Input/output support for processing in a mesh connected computer

An apparatus for processing data has a plurality of single-bit processing elements coupled together to form an m&times;n processing element array, where m is an integer number of rows and n is an integer number of columns. Each processing element has addressable storage for storing pixel data in an array format in which each addressable storage holds all of the bits associated with one pixel; and the processing element array includes a mechanism for providing direct read/write access to the addressable storage located in any addressed row of the processing element array without requiring that data be passed through other rows of the array. The apparatus also includes an addressable input/output memory for storing pixel data in a raster scan order; and pixel corner-turning logic, coupled to the input/output memory and to the processing element array, for transferring pixel data between the input/output memory and the processing element array, and for reordering bits of the pixel data being transferred so as to convert between the raster scan order and the array format.

Directly accessing local memories of array processors for improved real-time corner turning processing

Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant speed increases. Advantageously, however, the exemplary embodiments utilize logic and memory architectures which are fully compatible with, and fully useful for, conventional bit-serial applications, and the embodiments thus provide fast multiple-bit multiplications while at the same time providing all of the advantages typically associated with conventional bit-serial processors.

Methods and apparatus for performing fast multiplication operations in

An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a mask register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming 'supercells' within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register. These registers have bit values corresponding to respective columns (for the X Pattern register) and rows (for the Y Pattern register) of the array. Patterns can be propagated from these registers into corresponding rows and columns. Further these registers can be used to receive values representing the logical OR of signals generated by individual PEs within respective rows and columns. Further, a number of global data registers are used to store information which can be broadcast back into the processing array.

Pattern generation and shift plane operations for a mesh connected

A real-time image processor has three functional sections: an image manager, an image processor, and an instruction generator. The image processor may be an array of single-instruction multiple-data (SIMD) processing elements, for processing a subframe of sensor data. The instruction generator generates image processing commands for execution by the image processor. The image manager may be coupled to a plurality of sensors for simultaneously receiving streams of sensor data from the sensors, each stream constituting one or more image frames. When the image manager detects that a subframe of data has been received from a sensor, it loads that subframe into the image processor. Next, the image manager sends a message to the instruction generator, the message including a subframe ready indicator and an algorithm designator. In response, the instruction generator begins generating image processing commands that are determined by the algorithm designator. After the instruction generator has sent out the final image processing command for the designated algorithm, it notifies the image manager. In response, the image manager retrieves the processed image data from the image processor. Hit detection logic in the image manager identifies the location of processed data having predetermined values. The image manager can additionally use a reconstruction buffer to form a processed frame of data from separately processed subframes of data.

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Winter Park, FL, United States of America

Andrew P Abercrombie