Unisys Corporation

Andrew Neely

William G Burroughs

Richard L Fussell

Joseph A Manzella

A multiple-phase clock signal generator includes a phase-locked loop (PLL) for generating an oscillating signal having a predetermined frequency, a counter driven by the oscillating signal and having a plurality of outputs, and a plurality of combinational logic gates each having a plurality of inputs and an output. Selected ones of the inputs of each combinational logic gate are coupled to selected outputs of the counter to produce, at the output of each combinational logic gate, a clock signal having a particular phase. Different combinations of the outputs of the counter can be used to generate different phases.

Multiple-phase clock signal generator for integrated circuits,

A novel on-chip temperature sensing circuit includes a differential voltage source which comprises a plurality of branches each of which is provided with temperature sensitive transistor means. The differential output from the differential voltage source is coupled to the inputs of a high gain differential amplifier and the outputs from the high gain differential amplifier are connected to a second stage differential amplifer and one of the branches of the second stage differential amplifier is coupled to a high gain transistor amplifier which is connected to an output pin on the semiconductor chip so that the signal at the output pin is a noise tolerant voltage indication of the temperature of said semiconductor chip which may be monitored during actual online operations. A hysteresis feedback may be coupled between one of the outputs of the differential amplifiers to provide a hysteresis feedback loop and rapid switching of the second differential amplifier.

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Phoenixville, PA, United States of America

Andrew Neely