Hewlett-packard Company

Apollo Computer Inc.

Andrew Milia

Richard G Bahr

Barry J Flahive

A method and apparatus for selectively invalidating tag data related to data stored in high speed processor cache memory systems. The tag data to be invalidated, due to processor operations and cache memory misses, is stored in two tag stores and indicia related to the tag data to be invalidated is stored in a purge queue. Further improvement in system performance is provided by selective tag data and indicia elimination.

Duplicate tag store purge queue

A method and apparatus for granting, to a select processor in a multiprocessor computing system, exclusive access to a bus for issuance of address, data and command signals thereover, wherein each processor includes bus lock request and bus lock assert elements which provide corresponding bus request and bus hold signals which are recognized by corresponding elements included in other processors connected to the bus. The bus lock according to the present invention assures the processor having lock status of privacy on the bus necessary to complete a specified operation without interruption from the other processors.

Multiprocessor bus locking system with a winning processor broadcasting

A decentralized, pipelined, synchronous bus arbitration scheme which allows almost completely fair arbitration between multiple devices competing for the use of a communication bus while allowing the device that last used the bus faster access to the bus if no other device is competing for its use. The arbitration method and apparatus according to the present invention allows all competing devices equal access to the bus, with the exception that when bus requests are posted simultaneously, the device with the higher priority will always be granted use of the bus first.

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Burlington, MA, United States of America

Andrew Milia