Varian Semiconductor Equipment Associates, Inc.

Applied Materials, Inc.

Andrew Michael Waite

Rajesh Prasad

Stanislav S Todorov

Morgan Evans

Jonathan Gerald England

Johannes M Van Meer

Steven Robert Sherman

Kyu-Ha Shim

Jae Young Lee

Sungho Jo

Guy Oteri

Somchintana Norasetthekul

John J Hautala

Simon Ruffell

Hans-Joachim Ludwig Gossmann

Naushad K Variam

Wei Zou

Yuri Erokhin

Supakit Charnvanichborikarn

Cao-Minh Vincent Lu

Ana Cristina Gomez Herrero

Younki Kim

A method of processing a semiconductor substrate, including performing a first ion implantation process on the substrate, wherein a first ion beam formed of an ionized first dopant species is directed at a top surface of the substrate and is blocked from a first portion of the substrate while being allowed to implant a second portion of the substrate, and performing a second ion implantation process on the substrate, wherein a second ion beam formed of an ionized second dopant species is directed at the top surface of the substrate and is blocked from the first portion of the substrate while being allowed to implant the second portion of the substrate, wherein an effect of the second ion implantation process on an oxidation rate of the second portion counteracts an effect of the first ion implantation process on the oxidation rate of the second portion.

Method for precision oxidation control by ion implantation

Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars.

Implant to form vertical FETs with self-aligned drain spacer and junction

In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

Enhanced etch resistance for insulator layers implanted with low energy ions

Disclosed are methods for forming a semiconductor device. In some embodiments, a method may include providing a gate structure atop a substrate, providing a gate spacer along a sidewall of the gate structure, and performing a first ion implant to the gate structure and the gate spacer, the first ion implant comprising a thermal implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include performing a second ion implant to the gate structure and the gate spacer, the second ion implant including a room-temperature ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, and etching the gate structure and the gate spacer to remove just the second section of the gate spacer.

Asymmetric gate spacer formation using multiple ion implants

A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.

Techniques and structure for forming thin silicon-on-insulator materials

As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.

Etch rate modulation through ion implantation

A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality of fin structures coated with an oxide layer, wherein as a result of the CMP etch, a first portion of the oxide layer is removed, and the fin structures remain covered with oxide. The method may further include performing a selective area processing (SAP) etch using ions, wherein a second portion of the oxide layer is removed in a non-uniform manner, wherein after the SAP etch, the fin structures remain covered with oxide.

Techniques for forming isolation structures in a substrate

A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices.

Masking for high temperature implants

Various methods for implanting dopant ions into a three dimensional feature of a semiconductor wafer are disclosed. The implant temperature may be varied to insure that the three dimensional feature, after implant, has a crystalline inner core, which is surrounded by an amorphized surface layer. The crystalline core provides a template from which the crystalline structure for the rest of the feature can be regrown. In some embodiments, the implant energy and the implant temperature may each be modified to achieve the desired crystalline inner core with the surrounding amorphized surface layer.

Ion implant for defect control

A method of doping the polycrystalline channel in a vertical FLASH device is disclosed. This method uses a plurality of high energy ion implants to dope the channel at various depths of the channel. In some embodiments, these ion implants are performed at an angle offset from the normal direction, such that the implanted ions pass through at least a portion of the surrounding ONO stack. By passing through the ONO stack, the distribution of ranges reached by each ion may differ from that created by a vertical implant.

Method of doping a polycrystalline transistor channel for vertical NAND devices

Methods to implant ions into the sidewall of a three dimensional high aspect ratio feature, such as a trench or via, are disclosed. The methods utilize a phenomenon known as knock-in, which causes a first species of ions, already disposed in the fill material, to become implanted in the sidewall when these ions are struck by ions of a second species being implanted into the fill material. In some embodiments, these first species and second species have similar masses to facilitate knock-in. In some embodiments, the entire hole is not completely filled with fill material. Rather, some fill material is deposited, an ion implant is performed to cause knock-in to the sidewall adjacent to the deposited fill material, and the process is repeated until the hole is filled.

Method of implanting high aspect ratio features

A method of treating a CMOS device. The method may include providing a first stress liner on a transistor of a first dopant type in the CMOS device. The method may further include exposing the CMOS device to first ions in a first exposure, the first ions configured to reduce contact resistance in a source/drain region of a transistor of a second dopant type.

Method and system for forming low contact resistance device

A method of modifying a shape of a cavity in a substrate. The method includes forming one or more cavities on a surface of the substrate between adjacent relief structures. The method also includes directing ions toward the substrate at a non-normal angle of incidence, wherein the ions strike an upper portion of a cavity sidewall, and wherein the ions do not strike a lower portion of the cavity sidewall. The method further includes etching the one or more cavities wherein the upper portion of a cavity sidewall etches more slowly than the lower portion of the sidewall cavity.

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Beverly, MA, United States of America

Andrew Michael Waite