Intel Corporation

Andrew McRonald

Brett Neal

Lee Genz

Neal Meyer

Ping Sun

Gene Garrison

Dennis J Miller

Hieu Trung Tran

Srithar Ramesh

Gregory M Daughtry

Howard L Elikan

Methods and apparatus to validate continuous signal phase matching in high-speed nets routed as differential pairs are described. In one embodiment, a primary net of a differential pair may be traversed to determine whether a design rule violation has occurred based on comparison of calculated trace lengths of the primary net and a secondary net against a threshold value. Other embodiments are also described.

Validating continuous signal phase matching in high-speed nets routed as differential pairs

Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, determination, if the distance is not within the first tolerance, of whether the distance is within a second tolerance, determination, if the distance is not within the first tolerance and is within the second tolerance, of whether the length of the segment of the first polyline is less than a first threshold, and to indicate that the first polyline and the second polyline are sufficiently spaced, if the distance is not within the first tolerance and is within the second tolerance, and if the length of the segment of the first polyline is less than the first threshold.

Checks for signal lines

Design checks for signal lines

A first circuit layout design is obtained, and a second circuit layout design is obtained. A first topology graph is generated for the first circuit layout design, and a second topology graph is generated for the second circuit layout design. The first topology graph and the second topology graph are compared to obtain a comparison result. The comparison result is reported.

Comparison of circuit layout designs

A method and apparatus to adaptively validate a physical net routing topology of a substrate design to a target topology of the substrate design. A tree data structure is generated by mapping physical net routing topology objects to tree data structure objects the tree data structure representing the substrate design. The tree data structure is then compressed to form a compressed tree data structure. The compressed tree data structure is validated by comparing the target topology with the compressed tree data structure to determine if the target topology is electrically equivalent to the compressed tree data structure. One or more branches of the validated tree data structure is named, and the validated tree data structure is partitioned and saved.

Method and apparatus to adaptively validate a physical net routing topology of a substrate design

A system to evaluate a distance between polyline segments includes identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, and, if the distance is not within the first tolerance, determining whether the distance is within a second tolerance. If the distance is not within the first tolerance and is within the second tolerance, it is determined whether the length of the segment of the first polyline is less than a first threshold. If the distance is not within the first tolerance and is within the second tolerance, and if the length of the segment of the first polyline is less than the first threshold, it is indicated that the first polyline and the second polyline are sufficiently spaced. If the distance is not within the second tolerance or if the length of the segment of the first polyline is greater than the first threshold, it is determined whether the segments are located near a device pin, and, if the segments are not located near a device pin, it is indicated that the first polyline and the second polyline are not sufficiently spaced.

Method and system to evaluate signal line spacing

A method and apparatus for eliminating contention with dual masters. One method disclosed disables a default bus master, and tests for a second bus master. If the second bus master fails to respond, the default bus master is enabled.

Growing community of inventors

Beaverton, OR, United States of America

Andrew McRonald