Altera Corporation

Intel Corporation

Andrew Martyn Draper

Roger May

Edward H Flaherty

Andrew Crosland

Sean R Atsatt

Paul Metzgen

Ting Lu

Neil Kenneth Thorne

Ned M Smith

Kerry S Veenstra

Scott J Weber

Kent Orthner

Kulwinder Singh Dhanoa

Aaron Ferrucci

Timothy Allen

Andrew J Bellis

Desmond Leslie Ambrose

Iain Scott

Paul Riley

Sankaran M Menon

James Tyson

Xiaoyu Ruan

Yi Peng

Eric Innis

Chris Dettmar

Steve Tuyen Vu

Stephane Cauneau

Clive Davies

Jose Benchimol

David Samuel Goldman

Russell A James

Wei Chun Lau

Nathan Edward Krueger

Kenneth Chen

Fabio P Sousa

Fabio Petrassem De Sousa

Stephane Caneau

An apparatus is disclosed. The apparatus comprises one or more processors to receive a request to perform a firmware update at a device, prepare a second trusted compute base (TCB) layer for the firmware update, generate a first compound device identifier (CDI) associated with a first TCB layer to be used by the second TCB layer to attest an operational state of the first TCB layer prior to applying the update and generate a second CDI associated with the first TCB layer to be used by the second TCB layer to attest the operational state of the first layer after the update has been applied and perform the firmware update of the second TCB layer.

Seamless firmware update mechanism

An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.

Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device

Various examples of device and system implementations and methods for performing end-to-end attestation operations for multi-layer hardware devices are disclosed. In an example, attestation operations are performed by a verifier, including: obtaining layered attestation evidence regarding a state of a compute device, with the layered attestation evidence including attesting evidence provided from a second hardware layer of the compute device, such that the attesting evidence provided from the second hardware layer is generated from attesting evidence provided from a first hardware layer of the compute device to the second hardware layer of the compute device; obtaining endorsement information relating to the layered attestation evidence for the state of the compute device; determining an appraisal policy for performing attestation of the compute device from the layered attestation evidence; and applying the appraisal policy and the endorsement information to the layered attestation evidence, to perform attestation of the compute device.

End-to-end device attestation

A programmable logic device verifies that configuration data permissibly programs the programmable logic device. The programmable logic device includes a programmable fabric having partitions to be programmed by the configuration data, a secure device manager that may generate masks based on the configuration data, and a local sector manager. The masks determine that the configuration data is configured to permissibly program the permitted partitions or that the permitted partitions have been permissibly programmed. The local sector manager applies the masks to generate an interleaved result, compares the interleaved result to an expected result, and sends an indication that the configuration data is configured to permissibly program the permitted partitions or permissibly programmed the permitted partitions in response to determining that the interleaved result is the expected result, or sends an alert to stop programming in response to determining that the interleaved result is not the expected result.

On-device bitstream validation

The disclosed systems and methods may secure the fuse programming process in programmable devices to reduce or eliminate malicious discovery of data (e.g., the encryption key, the configuration bitstream) stored in nonvolatile memory via side-channel attacks. A processor may generate a randomized fuse list and the fuses may be blown in the randomized order. Additionally or alternatively, the processor may randomize the wait time between programming of each fuse. Further, the processor may generate a simplified fuse list including only fuses to be blown. The disclosed security systems and methods may be used individually or in combination to prevent determination of sensitive data, such as the encryption key, by monitoring, for example, power consumption in side-channel attacks.

Side-channel attack resistant fuse programming

Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a partition. Reconfiguring the programmable fabric also includes creating a mask for the partition that indicates that the identified resources belong to the partition. Reconfiguring the partition also includes reconfiguring resources, via a configuration controller, in programmable fabric associated with the partition using the mask without changing resources associated with other partitions in the programmable fabric.

Regional partial reconfiguration of a programmable device

An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via logic signals. The JTAG system includes a JTAG interface that receives logic signals and a first JTAG hub instantiated in the first partition communicatively coupled to the JTAG interface. The integrated circuit device further includes a second JTAG hub instantiated in the second partition communicatively coupled to the first JTAG hub via a bridge.

Sharing a JTAG interface among multiple partitions

A system for maintaining reconfigurable partitions in an integrated device includes a first buffer having channels that store configuration data and a mask. The system also includes first decompression circuitry having a second buffer coupled to the first buffer that stores the configuration data and second decompression circuitry having a third buffer coupled to the first buffer that stores the mask. The system also includes partition maintenance circuitry that applies the mask to the configuration data after the first decompression circuitry has decompressed the configuration data and the second decompression circuitry has decompressed the mask.

Maintaining reconfigurable partitions in a programmable device

An integrated circuit device such as a programmable integrated circuit may include interface circuits and associated identification circuits. The identification circuits may be coupled to shared mixer circuitry that performs a logic function on mixer input signals received from the identification circuits of that integrated circuit to produce a mixer output signal. Debug computing equipment may be used to test integrated circuits having mixer circuitry. The debug computing equipment may have interfaces that receive connections to interface circuits of the integrated circuits. The debug computing equipment may communicate with the mixer circuitry of the integrated circuits through each of the connected interface circuits to identify groups of interfaces that are connected to different devices. For each device, the debug computing equipment may select an interface from the corresponding group of interfaces and perform test debug operations over the selected interface.

System and methods for debug connectivity discovery

Various embodiments of the present disclosure enable interoperability between multiple codecs of various standards, notwithstanding that the number and type of standards in use at any particular time may vary unpredictably. A control unit, for example, a multipoint control unit (MCU) of a videoconference system, includes a partially reconfigurable programmable logic device (PLD). The PLD may include a reconfigurable region and a non-reconfigurable portion. The non-reconfigurable portion may include logic blocks for performing codec operations that are common across at least two codec standards. A selected subset a number of personas may be instantiated within the reconfigurable region of the PLD, each persona of the selected subset being compatible with at least a portion of the associated codec of at least one communication channel. The MCU selects, from between two or more personas, the selected subset of personas to be used within the reconfigurable region of the PLD.

Using FPGA partial reconfiguration for codec applications

According to various embodiments, a programmable device assembly includes an FPGA coupled to a nonvolatile serial configuration memory (e.g., serial flash memory) and a volatile fast bulk memory (e.g., SRAM or SDRAM). The nonvolatile serial configuration memory contains both the FPGA configuration data and CPU instructions. When a predetermined condition occurs, a serial memory access component that is hard coded on the FPGA automatically reads the configuration data from the nonvolatile serial configuration memory. The configuration data is used to configure the FPGA with various components, including a CPU, a boot ROM with code for a boot copier, and a bus structure. When the CPU boots, code for the boot copier is executed so that the CPU instructions are copied from the nonvolatile serial configuration memory to the volatile fast bulk memory. The CPU then executes the CPU instructions stored in the volatile fast bulk memory.

Booting mechanism for FPGA-based embedded system

Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port. When the second port is accessing the first plurality of memory cells, the arbiter prevents the first port from accessing the first plurality of memory cells, and when the second port is accessing the first plurality of memory cells, the arbiter allows the first port to access the second plurality of memory cells.

Embedded processor with dual-port SRAM for programmable logic

Methods and apparatus are provided for allowing flexible on-chip datapath interfaces on a device. Datapath connections allow data streamlining without any knowledge of channels or packet boundaries. Flexible and modular interface adapters are used to allow component designers to efficiently provide interoperable components without having to adhere to a strict datapath interface specification. Interface adapters from an adapter library are instantiated and configured automatically when two components are connected.

Flexible on-chip datapath interface having first and second component interfaces wherein communication is determined based on a type of credit condition

Flexible on-chip datapath interface for facilitating communication between first and second interfaces with different interface properties

Growing community of inventors

Chesham, United Kingdom

Andrew Martyn Draper