Texas Instruments Corporation

The University of Texas System

University of Nebraska

Intel Corporation

The State University of New York

University of California

Georgia Tech Research Corporation

Indiana University

Andrew Marshall

Theodore Warren Houston

Peter A Dowben

Howard L Tigelaar

Dmitri E Nikonov

Cloves Rinn Cleavelin

Tito Gelsomini

Harvey Davis

Joseph A Devore

Thomas A Schmidt

Jonathan Bird

Nishtha Sharma Gaul

Ross Eliot Teggatz

Weize W Xiong

Ashesh Parikh

James Robert Todd

Joe R Trogolo

Jingwei Xu

Eric G Soenen

Vijay Kumar Reddy

Stephanie Watts Butler

Gabriel George Barna

Makarand Ramkrishna Kulkarni

Victor C Sutcliffe

Kenneth G Buss

Karan Singh Bhatia

Wayne T Chen

David Barry Scott

David John Baldwin

Brian Keith Kirkpatrick

Siraj Akhtar

Ping Jiang

Srikanth Krishnan

Sumanth Katte Gururajarao

Stephen C Kwan

Ricky Dale Jordanger

Douglas A Prinslow

David R Cotton

Wei Dong

Youngmin Kim

Douglas E Mercer

David Brian Aldrich

Harvey J Stiegler

George Ernest Harris

Keith M Jarreau

Luan A Dang

Azad Naeemi

Pauline Poyun Wang

Frank L Thiel, V

Joe A Devore

Charles Weinberger

Sreedhar Natarajan

Michelle N Nguyen

Madhu Sayala

Andrew J Yost

Xuanyuan Jiang

Thilini K Ekanayaka

Guanhua Hao

Xiaoshan Xu

Nishtha Sharma

Ujas Natvarlal Patel

C Keith Burgess

Ruihua Cheng

Md Imran Hossain

Ching L Lin

Travis Summerlin

Uttam Singisetti

Raymond T Summerlin

Alpha T N'Diaye

Aaron Mosey

Harvey Edd Davis

A thin film molecular memory is provided that satisfies criteria needed to make a molecular spintronic device, based on spin crossover complexes, competitive with silicon technology. These criteria include, device implementation, a low coercive voltage (less than 1V) and low write peak currents (on the order of 10A/cm), a device on/off ratio >10, thin film quality, the ability to 'lock' the spin state (providing nonvolatility), the ability to isothermally “unlock” and switch the spin state with voltage, conductance change with spin state, room temperature and above room temperature operation, an on-state device resistivity less than 1 Ω·cm, a device fast switching speed (less than 100 ps), device endurance (on the order of 10switches without degradation), and the ability of having a device with a transistor channel width of 10 nm or below.

Thin film molecular memory

A magneto-electric (ME) majority gate device includes a conducting device and a plurality of ME transistors coupled to the conducting device. In one implementation, the plurality of ME transistors include a ME AND gate device with downward interface polarization, a ME-transmission gate device with downward interface polarization, and a ME-XNOR gate device. In another implementation, the plurality of ME transistors is five single-input ME-FETs.

Magnetoelectric majority gate device

A magneto-electric (ME) XNOR logic gate device includes a conducting device; and a ME-FET coupled to the conducting device. The ME-FET can be formed of a split gate; a first gate terminal coupled to a first portion of the split gate for receiving a first input signal; a second gate terminal coupled to a second portion of the split gate for receiving a second input signal; a source terminal coupled to a ground line; and a drain terminal coupled to the conducting device.

Magnetoelectric XNOR logic gate device

A magneto-electric (ME) inverter includes two anti-ferromagnetic spin orbit read (AFSOR) circuit elements, each AFSOR circuit element has a CMOS inverter; and an AFSOR device with a ME base layer; a semiconductor channel layer on the ME base layer and comprising a source terminal and a drain terminal, where the source terminal is coupled to an output of the CMOS inverter; and a gate electrode on the semiconductor channel layer. The gate electrode of a second AFSOR device of the two AFSOR circuit elements is coupled to the drain terminal of a first AFSOR device of the two AFSOR circuit elements.

Magnetoelectric inverter

Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.

Circuits based on magnetoelectric transistor devices

A magneto-electric magnetic tunnel junction device (ME-MTJ) that permits direct driving of ME-MTJ devices by a prior ME-MTJ device is the unipolar magneto-electric magnetic tunnel junction (UMMTJ) device. The UMMTJ device enables full logic circuitry to be implemented without level shifting between each logic element.

Unipolar magnetoelectric magnetic tunnel junction

An analog differential amplifier circuit, such as an operational transconductance amplifier (OTA), with input offset correction capability. First and second analog floating gate (AFG) devices each include a trim transistor connected in parallel with a series transistor in first and second input legs, respectively, of the amplifier. Floating gate electrodes in the AFG devices are differentially programmed to correct for error in the output signal in response to zero input differential voltage at its inputs. Temperature stability is attained by programming the floating gate electrodes to gate voltages above the floating gate transistors. In one embodiment, the AFG devices each include a second trim transistor sharing the same floating gate electrode; the sum of the currents conducted by the second trim transistors is added, by way of a current mirror, to the tail current applied to the first and second input legs.

Mismatch correction in differential amplifiers using analog floating gate transistors

An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.

Method to match SOI transistors using a local heater element

A configurable ME MTJ XOR/XNOR gate includes an insulator separating a top and bottom FM layer, a top ME layer with a first boundary magnetism at an interface of the top ME layer and the top FM layer, a bottom ME layer with a second boundary magnetism at an interface of the bottom ME layer and the bottom FM layer, and a top electrode coupled to the top ME layer and a bottom electrode coupled to the bottom ME layer. A voltage between the top electrode and FM layer is a first input, a voltage between the bottom electrode and FM layer is a second input, and a resistance between the top and bottom FM layer is indicative of the XOR or the XNOR of the inputs. The configurable ME MTJ XOR/XNOR gate has reduced energy consumption, smaller area, faster switching times, is non-volatile, and is configurable.

Configurable exclusive-OR / exclusive-NOR gate using magneto-electric tunnel junctions

A method of evaluating at least one parameter of a first capacitor. The method couples a number of capacitors in a capacitor network to a common node, the number of capacitors comprising at least three capacitors. Further, the method first applies a first voltage range to the capacitor network for causing a first voltage drop across the first capacitor, and it evaluates the at least one parameter in response to the first voltage range. The method second applies a second voltage range to the capacitor network for causing a second voltage drop across the first capacitor, the second voltage drop greater than the first voltage drop, and it evaluates the at least one parameter in response to the second voltage range.

Capacitor combination stress testing

A magneto-electric (ME) magnetic tunnel junction (MTJ) Exclusive-OR (XOR) gate is provided. The ME MTJ XOR gate includes an insulator separating a top ferromagnetic (FM) layer and a bottom FM layer, a top ME layer on the top FM layer, and a bottom ME layer on the bottom FM layer. The ME MTJ XOR gate also includes a top electrode coupled to the top ME layer and a bottom electrode coupled to the bottom ME layer where a voltage between the top electrode and the top FM layer is a first input, a voltage between the bottom electrode and the bottom FM layer is a second input, and a resistance between the top FM layer and the bottom FM layer is indicative of the XOR of the first input and the second input. The ME MTJ XOR has reduced energy consumption, smaller area, faster switching times, and is non-volatile.

Exclusive-OR gate using magneto-electric tunnel junctions

A non-volatile memory circuit includes an SRAM cell with magnetoelectric or ferroelectric structures for maintaining data within the SRAM cell even with power off. In some implementations, the magnetoelectric and ferroelectric structures can be programmed using a NOR or tristate gate coupled to an internal state of the SRAM cell. In other implementations, the magnetoelectric and ferroelectric structures can be configured as programmable resistors in the cross-coupled signal path of the SRAM inverters.

Non-volatile latch using magneto-electric and ferro-electric tunnel junctions

Majority and minority logic can be implemented by voltage controlled switching of magneto-electric layers of magneto electric magnetic tunnel junction (ME-MTJ) devices. A ME-MTJ device includes an exchange bias-controlled switching element and a pinned ferromagnetic layer on an antiferromagnetic layer. In one case, the switching element includes a magneto electric (ME) layer on a free ferromagnetic (FM) layer, and is separated from the pinned FM layer by an insulator. To implement a majority or minority logic gate a single ME-MTJ device may be used where the device is provided with three electrodes contacting the ME layer in an overlaying relationship with the ME layer. The orientation of the pinned FM layer indicates whether the gate is a majority or a minority logic gate.

Majority- and minority-gate logic schemes based on magneto-electric devices

A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor.

Body bias coordinator, method of coordinating a body bias and sub-circuit power supply employing the same

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Andrew Marshall