Cadence Design Systems, Inc.

Andrew Mark Chapman

Zhuo Li

Charles Jay Alpert

Andrew Hall

David Allan White

Natarajan Viswanathan

Mehmet Can Yildiz

Gracieli Posser

Thomas Andrew Newton

William Robert Reece

Ruth Patricia Jackson

A clock tree generated through clock tree synthesis (CTS) for an integrated circuit (IC) design is stored in memory. The IC design includes a post post-CTS clock tree that includes a plurality of clock nets. A request to add a user-specified clock instance to the post-CTS clock tree is received and all logically equivalent clock nets in the post-CTS clock tree detected to generate a set of candidate clock nets. A reduced set of candidate clock nets is generated from the set of candidate clock nets based on a distance between each candidate clock net and the clock instance. One candidate clock net in the reduced set is selected based on a length of conductive traces required to interconnect the corresponding candidate clock net and the clock instance. The post-CTS clock tree is restructured to connect the clock instance to the selected one of the candidate clock nets.

Restructuring algorithm for including user-specified clock instances in a post-CTS clock tree

Methods and systems for performing post clock tree synthesis of a clock tree. The methods and systems access, from memory, a circuit design comprising a clock tree that interconnects a clock source to a plurality of clock sinks, each clock sink in the plurality of clock sinks having an associated target insertion delay adjustment, the clock tree comprising a restriction on a quantity of levels of components for respectively adding delay to the clock source. The methods and systems identify an individual target insertion delay adjustment associated with an individual clock sink of the plurality of clock sinks and compare the individual target insertion delay adjustment to a threshold value. The methods and systems selectively remove the restriction on the quantity of levels of components to provide the individual target insertion delay adjustment based on comparing the individual target insertion delay adjustment to the threshold value.

Skewing level limited clock tree

Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the mean insertion delay and a target insertion delay adjustment determined for each individual clock sink. One or more clock sinks are identified that have a target insertion delay adjustment exceeding a skew threshold value. The clock tree is modified to reduce the target insertion delay adjustment, for each identified clock sink of the one or more clock sinks, to less than or equal to the skew threshold value.

Post-CTS insertion delay and skew target reformulation of clock tree

Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.

Post-CTS clock tree restructuring

A system for performing operations including accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a current timing offset of the clock tree to a target timing offset. The clock tree is modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to generate an updated clock tree. During modification, the first and second locations are analyzed to determine a load reduction and increase at the respective terminals. One or more neighboring clock tree instances are adjusted to compensate for the load reduction and increase. The operations include providing an indication that the clock tree has been updated and complies with the target timing offset.

Post-CTS clock tree restructuring with ripple move

Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.

Modifying route topology to fix clock tree violations

Aspects of the present disclosure address improved systems and methods for runtime efficient circuit placement location selection as described herein. An example embodiment includes identifying, for each route of the one or more routes that interconnect the terminals of a circuit design with the one or more pins of a first circuit element, a corresponding set of movement positions along said each route to generate a set of movement configurations for the first circuit element. The set of movement configurations is analyzed to generate a plurality of location clusters from the set of movement configurations, and for each location cluster of the plurality of location clusters, identifying one or more selected movement configurations within said each cluster. The one or more selected movement configurations for said each cluster to select an updated movement configuration.

Runtime efficient circuit placement search location selection

Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

Clock gate placement with data path awareness

Aspects of the present disclosure address improved systems and methods for core-route-based clock tree wirelength reduction. A method may include accessing an integrated circuit design comprising a clock tree comprising routes that interconnect terminals of a plurality of clock tree instances. The method further includes identifying a core route in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and the core route and determining a second offset based on a distance from the second terminal to the core route. The method further includes determining a target offset based on a combination of the first and second offsets and moving the clock tree instance toward the core route by the target offset.

Clock tree optimization by moving instances toward core route

Aspects of the present disclosure address systems and methods for shortening clock tree wirelength based on target offsets in connected routes. A method may include accessing a clock tree comprising routes that interconnect a plurality of pins. Each pin corresponds to a terminal of a clock tree instance. The method further includes identifying a first and second terminal of a clock tree instance in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and a branch in a first route connected to the first terminal and determining a second offset based on a distance between the second terminal and a branch in a second route connected to the second terminal. The method further includes moving the clock tree instance from a first location to a second location based on a target offset determined by comparing the first and second offsets.

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Milton, United Kingdom

Andrew Mark Chapman