Xilinx, Inc.

Andrew M Whyte

Richard Lewis Walke

Andrew Dow

Gordon I Old

Nihat E Tunali

Igor Kostarnov

Embodiments herein describe an FFT that can bypass one or more stages when processing smaller frames. For example, when all the stages in the FFT are active, the FFT can process up to a maximum supported point size. However, the particular application may only every send smaller sized frames to the FFT. Instead of unnecessarily passing these frames through the beginning stages of the FFT (which adds latency and consumes power), the embodiments herein can bypass the unneeded stages which reduces the maximum point size the FFT can process but saves power and reduces latency. For example, the FFT can have selection circuitry (e.g., multiplexers) disposed between each stage that permits the input data to either bypass the previous stage(s) or the subsequent stage(s), depending on the architecture of the FFT. The bypassed stages can then be deactivated to conserve power.

Streaming FFT with bypass function

Embodiments herein describe, when executing an average pooling operation in a neural network, scaling input operands before performing an accumulate operation. Performing average pooling in a neural network averages the values in each face of a 3D volume, thereby downsampling or subsampling the data. This can be performed by adding all the values in a face and then dividing the total accumulated value by the total values in the face. However, the order of operations in a multiply-accumulator (MAC) is reversed from the order of operations for performing average pooling. To more efficiently use the MAC, the order of operations when performing average pooling is reversed so that determining the average value for a face can be performed on a single MAC. To do so, the values in the face are first scaled by a multiplier before being summed by an accumulator.

Average pooling in a neural network

A decoder circuit includes a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes and an LDPC code configurator to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The decoder circuit further includes an LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository.

Low-density parity-check (LDPC) encode using an LDPC decoder

A decoder circuit can include low-density parity-check (LDPC) decoder circuitry having a plurality of stages and an LDPC repository configured to store parity-check information associated with one or more LDPC codes. The LDPC repository is configured to determine a stall requirement for a layer of a first data block and perform a memory check for a second data block. The LDPC repository, in response to the stall requirement indicating a stall for the layer of the first data block and determining that the memory check is satisfied, is further configured to schedule processing of the first data block and the second data block in the LDPC decoder circuitry using the parity-check information by interleaving the layer of the first data block and a layer of the second data block through the plurality of stages of the LDPC decoder circuitry.

Interleaved data block processing in low-density parity-check (LDPC) encoder and decoder

A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read address signal. The memory is configured to receive a first plurality of write addresses, from the write address signal, including a first plurality of addresses of the memory in a first order, and write, to the first plurality of write addresses, a first plurality of data words during a first time period. The memory is further configured to receive a first plurality of read addresses, from the read address signal, including the first plurality of addresses in a second order, and read, from the first plurality of read addresses, the first plurality of data words during a second time period. The first and second time periods partially overlap. The first order may be one of a natural order and a modified order, with the second order being the other of the natural order and the modified order, and the modified order may be one of a bit-reversed order and a digit-reversed order. The memory may have different write modes, and may be a read-before-write memory or a write-before-read memory.

Systems and method for buffering data using a delayed write data signal and a memory receiving write addresses in a first order and read addresses in a second order

An apparatus relating generally to accumulation is disclosed. In this apparatus, a first subtraction-bypass stage is coupled to receive an input operand and a modulus operand to provide a first difference and the input operand. An accumulation stage is coupled to the first subtraction-bypass stage to receive the first difference and the input operand. The accumulation stage is coupled to receive an offset operand for providing an offset-accumulated result. A second subtraction-bypass stage is coupled to receive the offset operand and the modulus operand to provide a second difference and the offset operand. A consolidation stage is coupled to receive the offset operand, the second difference and the offset-accumulated result to provide a consolidated accumulated result. The first subtraction-bypass stage, the accumulation stage, the second subtraction-bypass stage, and the consolidation stage are for a redundant number system.

Pipelined phase accumulator

A circuit structure efficiently multiplies a first and second number. The circuit structure includes multipliers for the pairs of three-bit digits of the first number and three-bit digits of the second number. The multipliers produce six-bit partial products from the pair of three-bit digits of the first and second numbers. Each multiplier includes look-up tables receiving the pair of three-bit digits of the first and second numbers. A summing-tree circuit includes adders arranged in a series of levels, the adders in an initial one of the levels producing partial sums from the six-bit partial products from the multipliers, and for each first and successive second ones of the levels in the series, the adders in the second level producing another plurality of partial sums from the partial sums from the first level. A last one of the levels includes the adder that produces a product of the first and second numbers.

Circuit structure for multiplying numbers using look-up tables and adders

An efficient circuit and method for performing radix-3 Discrete Fourier transform (DFT) of a 3*2size data frame are provided. The data frame is split and fast Fourier transform (FFT) processed as three sub-frames. Radix-3 operations are performed on the FFT processed sub-frames over a number of stages with time shared hardware to compute the DFT of the data-frame. FFT operations are performed on the second and third sub-frames to produce respective sub-transforms. Concurrently with FFT processing of the first sub-frame, butterfly operations are performed on the sub-transforms of the second and third sub-frames. Through the use of time-shared hardware and arranging FFT operations to correspond with radix-3 operations at various stages of processing, the DFT is performed with existing FFT processors while reducing resource requirements and/or reducing DFT transform time over the full-parallel radix-3 implementation.

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Edinburgh, United Kingdom

Andrew M Whyte