U.S. Philips Corporation

Koninklijke Philips Corporation N.V.

Philips Electronics North America Corporation

Andrew M Warwick

Theodore James Letavic

Mark Simpson

Godefridus A M Hurkx

Andrew L Goodyear

Keith M Hutchings

Holger Schligtenhorst

Richard H Egloff

An insulated-gate field-effect semiconductor device, preferably of the SOI type, has source ( ) and drain ( ) regions in a semiconductor body portion ( ) at a first major surface of a semiconductor substrate ( ). The gate-terminal metallisation ( ) is present at an opposite second major surface ( ) of the substrate ( ). A gate connection ( ) is present between the gate electrode ( ) and the substrate ( ) to connect the gate electrode ( ) to the gate-terminal metallisation ( ). This arrangement permits better use of the layout area for source-terminal and drain-terminal metallisations, and their connections, at the upper major surface ( ) of the body portion ( ), without introducing an on-resistance penalty. The part of the gate connection provided by the substrate ( ) does not increase the on-resistance of the main current path through the device, i.e. between the source ( ) and drain ( ). Furthermore, a p-n junction diode can be readily integrated between the channel region ( ) and the gate connection ( ).

Insulated-gate field-effect semiconductor device

In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region ( ) of one conductivity type forms a switchable p-n junction ( ) with a second region ( ) of opposite conductivity type. In accordance with the invention, this first region ( ) includes three distinct zones, namely a low-doped zone ( ), a high-doped zone ( ), and an intermediate additional zone ( ). The low-doped zone ( ) is provided by a semiconductor body portion ( ) having a substantially uniform p-type doping concentration (P&minus;) and forms the p-n junction ( ) with the second region ( ). The distinct additional zone ( ) is present between the low-doped zone ( ) and the high-doped zone ( ). The high-doped zone ( ) which may form a contact zone has a doping concentration (P&plus;&plus;) which is higher than that of the low-doped zone ( ) and which decreases towards the low-doped zone ( ). The distinct additional zone ( ) has an additional doping concentration (P&plus;) which is lower than the doping concentration (P&plus;&plus;) of the high-doped zone ( ) and which decreases towards the low-doped zone ( ). This triple-zone formation for the first region ( ) permits an improvement in switching behaviour, e.g. in terms of fall-time and energy dissipation during turn-off of the device (T, D). A very low doping (P&minus;) can be used for low-doped zone ( ) so that, in the off-state of the device (T, D), this zone ( ) and also the additional zone ( ) can be fully depleted. The additional zone ( ) having its additional doping concentration provides a path for extracting residual charge carriers from the low-doped zone ( ) when the device (T, D) is being switched off.

Semiconductor switch devices having a region with three distinct zones and their manufacture

A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by a surface insulation region. In order to increase breakdown voltage and/or reduce &ldquo;on&rdquo; resistance, the lateral drift region is provided with at least a portion with a retrograde doping profile. This may advantageously be done by doping the semiconductor substrate, oxidizing the substrate to form the buried insulating layer, forming the SOI layer on the buried insulating layer, and thermally diffusing dopant from the buried insulating layer into the SOI layer.

Lateral thin-film silicon-on-insulator (SOI) device having a lateral drift region with a retrograde doping profile, and method of making such a device

A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7). The first and second masking layers (6 and 8) are removed and an insulated gate structure (10) is provided by defining a gate insulating layer (10a) on the recess walls (9a) and providing a gate conductive region (10b) on the insulating layer (10a). A relatively lowly doped third region (11) of the opposite conductivity type is provided to extend between the relatively highly doped second region (7) and the recess (9) to provide a conduction channel area (11a) adjacent the insulated gate structure (10). A fourth region (12) is provided to form a potential barrier (12a) with the relatively lowly doped third region (11) so that the conduction channel area (11a) provides a conductive path between the fourth and first regions (12 and 4).

Growing community of inventors

Stockport, United Kingdom

Andrew M Warwick