Intel Corporation

Andrew M Volk

Robert R Fulton

Chinnugounder Senthilkumar

Michael W Williams

Jen-Tai Hsu

David J McDonnell

Terry L Baucom

Amir Bashir

Ken Drottar

Ronald W Swartz

Jeff C Morriss

Puthiya K Nizar

Tea M Lee

Lawrence S Uzelac

Mukul Kelkar

David D Donofrio

Steve S Simoni

Michael D Piorun

Praveen Dani

David J Harriman

Sanjay Dabral

David Stewart Dunning

Huimin Chen

Andrew W Martwick

Ajay V Bhatt

Timothy J Maloney

Ming Zeng

Duane G Quiet

Robert J Johnston

Roger W Van Brunt

Zale Theodore Schoenborn

Warren Morrow

Sandeep K Jain

Joe Salmon

Vui Yong Liew

William B Pohlman

Sudarshan Bala Cadambi

David E Freker

Dennis J Miller

Romesh B Trivedi

Harishankar Sridharan

Prasanna C Shah

Pravas Pradhan

Shaun Knoll

Kevin E Arendt

Surya Musunuri

Eric B Selvin

Brent S Crittenden

Chris D Matthews

Richard M Haslam

Shelagh Ann Callahan

Jing Li

Sridhar Tirumalai

Sajjad A Zaidi

Naveed Khan

Garrett Hall

Vishnu Balraj

Hou-Sheng Lin

Ramesh Senthinathan

Christopher L McAfee

Katen A Shah

Vitnai Kam Leung

Roger V Brunt

Rajesh Kanakath

Hing-Yan To

Kevin M Hill

Tom J Schneider

Thomas To

Jennefer Asperheim

Tan T Wang

Generally, this disclosure describes a system and method for generating random numbers. In at least one embodiment described herein, the method may include generating random bits in accordance with at least one security application via an integrated circuit, said integrated circuit including a true random number generator having an analog core. The method may further include providing, via an internally generated power supply, power to said analog core via a voltage regulator associated with said true random number generator. Of course, additional operations are also within the scope of the present disclosure.

Random number generator

Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Spread spectrum clock generator

An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.

Synchronous frequency synthesizer

Transmitting a transition between high and low states across a lengthy conductor with a main transmitter to transmit data, providing emphasis with an emphasis transmitter to strengthen the transmission of the transition, transmitting a low-to-high transition to test for the absence of an electronic device coupled to the lengthy conductor, and detecting an occurrence of an overvoltage level indicating the absence of such an electronic device.

Signal drive de-emphasis control for serial bus

According to an embodiment of the invention, a method and apparatus for DC voltage conversion are described. According to one embodiment, a voltage converter comprises a current mirror, the current mirror being coupled with a power source; a first transistor device coupled with a bias generator to receive a bias voltage; a second transistor device coupled between the current mirror and the first transistor device; and an output transistor device, a gate of the output transistor device being coupled with a gate of the second transistor device and to the current mirror.

DC-to-DC voltage converter

In some embodiments, a chip includes clock generation circuitry to create a clock signal, and reference signal oscillator circuitry to produce a reference signal with a higher frequency than the clock signal. The chip includes a counter to change a count value in response to changes in the reference signal; and count logic circuitry to cause count storage circuitry to read the count value in response to at least some changes in the clock signal and to make at least some of the values in the count storage circuitry related to a duty cycle of the clock signal available to an external tester. Other embodiments are described and claimed.

Circuitry and method to measure a duty cycle of a clock signal

A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further apparatus, systems, and methods enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range.

Fast lock scheme for phase locked loops and delay locked loops

Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.

Method and apparatus for minimizing leakage current in semiconductor logic

In some embodiments, a phase detector receives a set of sampling clock signals and a data signal and compares each of the clock signals to the data signal. A clock selector selects an optimal sampling clock signal from the set of sampling clock signals based on a trend of a relationship between the clock signals and the data signal. Other embodiments are described and claimed.

Determining an optimal sampling clock

An apparatus and method for low latency power management on a serial data link are described. In one embodiment, the method includes the detection of an electrical idle exit condition during receiver operation in an electrical idle state. Once detected, data synchronization is performed according to one or more received data synchronization training patterns. Finally, when the synchronization is performed within a determined synchronization re-establishment period, the receiver will resume operation according to a normal power state. Accordingly, the embodiment described illustrates an open loop, low latency power resumption operation for power management within 3GIO links.

Apparatus and method for low latency power management on a serial data link

According to one embodiment, a voltage regulator system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load, and control logic coupled to the voltage regulator circuit. The control logic controls the voltage regulator circuit so that the voltage regulator circuit supplies power to the load if activated by the control logic and a core voltage power supply supplies power to the load if the voltage regulator circuit is de-activated by the control logic.

Mechanism to control an on die voltage regulator

Start-up circuit for current mirror circuits to facilitate transition from a zero-current state to an operation state. The start-up circuit includes two sets of current control devices. A set is coupled to each leg of the current mirrored circuit to provide a bias on start-up. The current control devices are coupled together to mirror the current that continues during the operational state such that the start-up circuit in combination with the operating circuit do not draw more current in the operational state than the operating circuit would normally draw in the operational state.

Low power start-up circuit for current mirror based reference generators

According to one embodiment, an integrated circuit (IC) is disclosed. The IC includes a package, a die mounted within the package, circuit components mounted on the die, and a voltage regulator mounted on the die to supply power to the circuit components.

On die voltage regulator

A delay element is coupled to a first interface, which is coupled to a second interface via interconnect. Traces in the interconnect for propagating output signals from the first interface to the second interface have varying lengths. In order to reduce undesirable effects resulting from simultaneously switching the output signals, the delay element programmably and selectably delays the output signals according to the lengths of the traces they respectively travel to the second interface. Additionally, the effect of varying lengths of interconnect on receiver timings can be accommodated by using the delay element to programmably and selectably sample data at a receiver interface.

Method and system for reducing the effects of simultaneously switching outputs

Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.

Synchronizing and aligning differing clock domains

Growing community of inventors

Granite Bay, CA, United States of America

Andrew M Volk