Ferranti Plc

Andrew M Mallinson

Adrian H Hoodless

A CRT display system providing a raster pattern, possibly for a flat screen CRT, has an oscillator driving a Line counter. The Line counter drives a Field counter and a Line DAC. The Field counter drives a Field DAC. In response, there are generated signals, representing functions, to be applied to the CRT deflection plates, and whereby there is represented the inverse of any function representing distortion of the raster pattern required to be corrected. At least one further DAC may be provided, comprising one of a pair of interacting DAC's, with one DAC driven by the Line counter, and one DAC driven by the Field counter, the output of said further DAC causing a combined function to be represented by the output of said other DAC. Said other DAC may comprise either the Line DAC, or the Field DAC; or said further DAC of another pair of interacting DAC's.

Cathode ray tube display systems

A CRT display system providing a raster pattern has digital means 30, 31, 32 to drive a DAC 34. In response, there are supplied analogue signals, on a line 37. There are also provided pulse generating means 90 controlled by the digital means, and integrating means comprising two integrators. Each integrator is connected individually to an X deflection plate 14 of the CRT, and comprises an amplifier and a feedback capacitor. One capacitor C2 is charged by negative-going pulses, and the other capacitor C2' is charged by positive-going pulses, until the pulses are removed, when the required ramps are applied to the deflection plates. Then a current flows through a transistor T7, and is controlled by the DAC output on the line 37. Hence, the waveforms applied to the deflection plates cause distortion of the raster pattern otherwise obtained, to be corrected, the DAC output representing a function comprising the inverse of the function representing the distortion.

A bipolar transistor logic circuit has a hierarchical arrangement of pairs of bipolar transistors, each pair of transistors having their emitters connected together, and the bases of at least some pairs receiving a differential input to the logic circuit. The highest level has only one pair of transistors, with their emitters connected to a constant current source. A differential output is provided on two lines, at least the collectors of the lowest level being coupled selectively to the lines. The arrangement is required to be symmetrical. In an otherwise non-symmetrical arrangement, the arrangement is made symmetrical by including dummy pairs of transistors not receiving a differential input. In performing a logical operation, the differential output, and the collector potentials of each pair of transistors start to vary in the appropriate sense. Further, there is a switch controlling the constant current source enabling the logic circuit to be driven ON and OFF so that the logic circuit starts each operation in the equilibrium condition. Hence the logic circuit is fast in operation. In one embodiment, the logic circuit also includes a latch having two parallel arms, each arm including an input transistor coupled to the hierarchical arrangement, and a switching transistor. The switching transistor collectors and bases are cross-coupled, and the emitters are connected together and to two parallel constant current sources. The output of one source is insufficient to drive the latch, but is sufficient to set the latch. The output of the other source is sufficient to drive the latch, and is connected to the switching transistors via controlled by timing means common also to the switch associated with the hierarchical arrangement.

Bipolar transistor logic circuits

A constant voltage circuit has two rails 10 and 12, with one rail 12 at a variable potential V, possibly supplied by a voltaic cell. In one arm between the rails there is voltage reference means Z1, 14, with a circuit output line 16 connected thereto, and the line 16 is required to be maintained at a potential V.sub.o, corresponding to a maximum value for V. In a second arm there is provided a first resistor R1, connected to the rail 12, and in series with a transistor T2. A second, equal, resistor R2 is connected between the output line 16 and the transistor T2. Means Z2, 30, T3, causes a potential, corresponding to the variable, decreasing, potential V, to be applied between the second resistor R2 and the transistor T2. The current to the transistor T2 is constant over a wide range dV for V, by a compensating current portion dI flowing through the second resistor R2, thereby maintaining V.sub. o constant. Usually, current gain means, such as a transistor T1, is provided, in the first arm, between the output line 16 and the rail 12.

Constant voltage circuits

A circuit for converting a TV receiver to operate in accordance with the system associated with received signals, there being either F or F' scan lines in a field, with F&lt;F', includes a counter driven by pulses each representative of one end of a raster scan line, and having M stages, with F and F'&lt;M&lt;2F and 2F'. There is also means to preload the counter selectively with a count of R or R', where (M-2R)=F and (M-2R')=F'. Wide window means detects when a field sync pulse is within a window including the (M-R)th and (M-R') stages, and, in response, the counter, initially, is preloaded with R'. Decision logic means then detects whether a field sync pulse occurs after the Kth stage, with K=M-[R+R']/2, when R' is continued to be preload; or occurs before the Kth stage, when R subsequently is preloaded; and the required TV receiver conversion is completed.

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Salem, NH, United States of America

Andrew M Mallinson