Texas Instruments Corporation

Andrew M Love

Roger D Norwood

Robert L Pitts

David V Kersh, Iii

Robert M Crosby

Clyde F Dunn

Lich X Dang

Mohammed A Hassan

A transparent latch ( ) and a logic conditioning circuit ( ) are disclosed. The transparent latch ( ) receives signals from conditioning circuit ( ), including a test input that indicates whether the transparent latch is in a testing mode or an operational mode. When the transparent latch ( ) is in a testing mode, the transparent latch acts as a buffer or flow-through logic circuitry, permitting the logic circuitry that includes transparent latch ( ) to be tested according to existing test methodologies. When the transparent latch is not in testing mode, the transparent latch ( ) acts as a transparent latch ( ), holding the state of the input when the clock signal is in a first state and allowing the input to propagate to the output when the clock signal is in a second state.

Testable transparent latch and method for testing logic circuitry that includes a testable transparent latch

In a Flash memory unit, the storage of a logic signal in the memory cells is determined by performing a READ operation. The NORMAL READ operation requires that the floating gate store an amount of charge Q above which a logic &ldquo;0&rdquo; is identified and below which a logic &ldquo;1&rdquo; is identified as being stored in the memory cell. A second level of charge Q stored on the floating gate is used in a TEST READ operation. The stored charge Q is greater than the stored charge Q , but less than the charge stored on the floating gate as the result of a WRITE operation. The result of a TEST READ operation is compared with a NORMAL READ operation of a memory cell. When the logic state identified by the TEST READ operation and the NORMAL READ operation are not the same, the charge on the cell is determined to have decayed below a prescribed level and the memory cell is refreshed to the level that is present during a WRITE operation.

Apparatus and method for refreshing a flash memory unit

A more efficient memory access is provided by providing fast access to words on the same physical row (wordline) in memory whether sequential or not, by, after issuance of an address, the detection of whether the current access is on the same physical memory row as the previous access and accordingly allows a different number of wait states, dependent on whether the access is on the same row or not.

Burst access memory system

In one embodiment, the pulse-generating circuit includes a triggering field-effect device having a source-drain path connected between a voltage supply and an internal node and having a gate connected to a source of reference potential, a capacitor connected between the voltage supply and the output node, and a detector field-effect device having a source-drain path connected between the output node and the source of reference potential and having a gate connected to the internal node. An optional load device, an optional pull-down device, an optional second capacitor, a optional string of diode-connected devices, and an optional feedback device may be included. Device channel lengths are specified for proper operation. In one embodiment, the circuit includes only a detector field-effect transistor and a load field-effect transistor, the detector transistor having a channel length substantially longer than the channel length of the load transistor. The circuit described and claimed herein is immune to the unpredictable behavior of static logic gates during the initial part of the power-on transient when the supply voltage is less than the threshold voltage of the integrated circuit transistors. In particular, the circuit does not have a node connected to both a static pull-up path and a static pull-down path, both of which are on at the same time, forming a linear circuit.

Method for generating power-up pulse

During an active phase of operation of the circuit (70), a gate (38) of a transistor (14) is boosted to a first voltage level that is substantially above the voltage supply level (V.sub.dd). After the gate (38) is boosted, the signal node (12) is boosted by transmitting current through the current path of the transistor (14) from a first electrode (16) of a boosting capacitor (18). During a reset phase of operation of the circuit (70), a second electrode (26) of the capacitor (18) is discharged. This causes the withdrawl of the charge from the signal node (12) through the current path of the transistor (14) to the first electrode (16) of the boosting capacitor (18). A predetermined voltage level near the voltage supply level is established across the electrodes (16, 26) of the boosting capacitor (18) in response to this. Finally, the transistor gate (38) is discharged to isolate the boosting capacitor (18) from the node (12 ), such that the desired voltage level is maintained across the boosting capacitor (18) for an extended length of time.

Charge-retaining signal boosting circuit and method

The described embodiments of the present invention provide a circuit and method for programming the mode options of an integrated circuit. The embodiment described provides this function for a dynamic random access memory but is applicable to any integrated circuit. The integrated circuit includes programming bonding pads which are either connected to a selected reference potential or left unconnected. Circuitry on the integrated circuit determines whether the pad is connected to the reference potential or is unconnected, and provides logical signals on the integrated circuit which select the operational mode of the integrated circuit. An additional feature of the described embodiment is a continuous checking to determine if the appropriate connected or unconnected state is being detected. This feature provides stray fields and other erroneous signals from altering the mode operation of the integrated circuit.

Bond programmable integrated circuit

A delay stage (60) has a delay period of reduced dependence on the level of a first voltage supply (V.sub.dd). First and second inverter stages (78, 90) each have p-channel transistors (68, 86) and n-channel transistors (70, 88). The gates (64, 66) of the first inverter pair are connected to an input node (62). A fixed resistor (72) is inserted between the current path of the p-channel transistor (68) of the first inverter pair and a signal node (76). The current path of the n-channel transistor (66) of the first inverter is operable to connect the signal node (76) to ground. A MOSFET capacitor (80) is coupled to the signal node (76), as are the gates (82, 84) of the second inverter transistor (86, 88). The current path of the p-channel transistor (86) of the second inverter is operable to connect the voltage supply (V.sub.dd) to an output node (92), and the current path of the n-channel transistor (88) of the second inverter (90) is operable to connect the output node (92) to ground. The trigger point of the second inverter stage (90) is chosen to be substantially the same as the difference between the voltage supply level and the threshold voltage of the transistor (86).

Delay stage with reduced V.sub.dd dependence

In one embodiment, the pulse-generating circuit includes a triggering field-effect device having a source-drain path connected between a voltage supply and an internal node and having a gate connected to a source of reference potential, a capacitor connected between the voltage supply and the output node, and a detector field-effect device having a source-drain path connected between the output node and the source of reference potential and having a gate connected to the internal node. An optional load device, an optional pull-down device, an optional second capacitor, an optional string of diode-connected devices, and an optional feedback device may be included. Device channel lengths are specified for proper operation. In one embodiment, the circuit includes only a detector field-effect transistor and a load field-effect transistor, the detector transistor having a channel length substantially longer than the channel length of the load transistor. The circuit described and claimed herein is immune to the unpredictable behavior of static logic gates during the initial part of the power-on transient when the supply voltage is less than the threshold voltage of the integrated circuit transistors. In particular, the circuit does not have a node connected to both a static pull-up path and a static pull-down path, both of which are on at the same time, forming a linear circuit.

Power-up pulse generator circuit

The described embodiments of the present invention provide a circuit and method for programming the mode options of an integrated circuit. The embodiment described provides this function for a dynamic random access memory but is applicable to any integrated circuit. The integrated circuit includes programming bonding pads which are either connected to a selected reference potential or left unconnected. Circuitry on the integrated circuit determines whether the pad is connected to the reference potential or is unconnected, and provides logical signals on the integrated circuit which select the operational mode of the integrated circuit. An additional feature of the described embodiment is a continuous checking to determine if the appropriate connected or unconnected state is being detected. This feature prevents stray fields and other erroneous signals from altering the mode operation of the integrated circuit.

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Stafford, TX, United States of America

Andrew M Love