Adeia Semiconductor Solutions LLC

Tessera LLC

Andrew M Greene

Rajasekhar Venigalla

Nicole A Saulnier

Siva Kanakasabapathy

Marc A Bergendahl

John R Sporre

Jeffrey Shearer

Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

FinFET gate cut after dummy gate removal

A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Gate cut with integrated etch stop layer

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Albany, NY, United States of America

Andrew M Greene