Rambus Inc.

Andrew M Fuller

Robert E Palmer

John Wood Poulton

Frederick Abbott Ware

Thomas J Giovannini

Michael D Bucher

Thoai Thai Le

Masum Hossain

Lei Luo

William Franklin Stonecypher

Barry William Daly

Hsuan-Jung Su

A lock-detection circuit detects whether a first clock signal is frequency locked to a second clock signal. A lock-detection scheme that continuously evaluates the lock condition between the clock signals and as programmable frequency-offset tolerances for reporting lock acquisition and loss. A quadrature clock generator produces two periodic signals from the first clock signal. The periodic signals are in quadrature, which is to say they are misaligned with one another by ninety degrees. These quadrature signals are sampled on edges of the second clock signal to produce a sequence of states that exhibit a Gray-code progression if first and second clock signals are locked. Errors in the Gray-code progression indicate whether edges of the first clock signal are early or late with respect to the second clock signal. The lock-detection circuit is adjustable to indicate loss of lock under in dependence upon the temporal spacing of errors.

Phase-based lock detector with programmable frequency offset tolerance

Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing-reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.

Circuits and methods for self-adaptive decision-feedback equalization in a memory system

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Memory controller operable in data loop-back mode

A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe signal according to the qualification values output from the FIFO storage structure.

Signal receiver with skew-tolerant strobe gating

Memory controller with looped-back calibration data receiver

An integrated circuit comprises a signal transmitter and a sampling circuit coupled to the signal transmitter, wherein the sampling circuit is to sample output voltage levels of an output of the signal transmitter at different respective times. The integrated circuit further comprises a measurement circuit coupled to the sampling circuit, wherein the measurement circuit is to compare the output voltage levels of the output of the signal transmitter to corresponding reference voltages to identify a first time when a first output voltage level equals a first reference voltage and a second time when a second output voltage level equals a second reference voltage. A time difference between the first time and the second time is used to configure a slew rate adjustment control of the signal transmitter.

Integrated transmitter slew rate calibration

A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.

Low-power multi-domain synchronizer

Memory IC with data loopback

Clock-forwarding memory controller with mesochronously-clocked signaling interface

Signaling interface with phase and framing calibration

In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.

Chip-to-chip signaling link timing calibration

A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver.

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Chapel Hill, NC, United States of America

Andrew M Fuller