University of Michigan

Arm Limited

Andrew Lukefahr

Scott Mahlke

Reetuparna Das

Shruti Padmanabha

Jiecao Yu

Ganesh Suryanarayan Dasika

David Palframan

Reetuparnda Das

Subject matter disclosed herein may relate to storage and/or processing of signals and/or states representative of neural network parameters in a computing device, and may relate more particularly to compressing signals and/or states representative of neural network nodes in a computing device.

Systems and devices for compressing neural network parameters

Subject matter disclosed herein may relate to storage of signals and/or states representative of parameters in a computing device, and may relate more particularly to storage of signals and/or states representative of neural network parameters in a computing device.

Systems and devices for formatting neural network parameters

A method, apparatus, and CRM that detect repetition of an out-of-order execution schedule for a group of instructions executed by an out-of-order processor. Data indicative of at least one performance metric for an instance of execution of said group of instructions by the out-of-order processor is determined. The determined data are compared with previous data of the at least one performance metric for at least one previous instance of execution of the group of instructions by the out-of-order processor. Repetition of the out-of-order execution schedule is detected dependent on the comparison.

Method of detecting repetition of an out-of-order execution schedule, apparatus and computer-readable medium

Apparatus and a corresponding method for controlling a transition between use of first processing circuitry and second processing circuitry to execute program instructions are provided. Transition monitoring storage selects an entry for a load program instruction executed during the transition in dependence on a memory address from which a value is to be loaded and stores a program order timestamp for the load program instruction, unless a valid previously stored program order timestamp in the entry precedes the program order timestamp. Thus the oldest timestamp of an load instruction executed in the transition is held. At either the start or end (or both) of the transition the content of the transition monitoring storage is cleared. When a store program instruction is executed during the transition and when a further program order timestamp for the store program instruction indicates that the store program instruction precedes in program order a load program instruction already executed in the transition, program instructions which follow the store program instruction in the first and second processing circuitry are squashed and re-executed. Data hazards which could otherwise arise during the transition are thus avoided by the use of transition monitoring storage which is nevertheless conveniently small.

Controlling transition between using first and second processing circuitry

An apparatus for processing data includes first execution circuitry, such as an out-of-order processor, and second execution circuitry, such as an in-order processor. The first execution circuitry is of higher performance but uses more energy than the second execution circuitry. Control circuitry switches between the first execution circuitry being active and the second execution circuitry being active. The control circuitry includes prediction circuitry which is configured to predict a predicted identity of a next sequence of program instructions to be executed in dependence upon a most recently executed sequence of program instructions and then in dependence upon this predicted identity to predict a predicted execution target corresponding to whether the next sequence of program instructions should be executed by the first execution circuitry or the second execution circuitry.

Recording performance metrics to predict future execution of large instruction sequences on either high or low performance execution circuitry

A data processing apparatus includes a first execution mechanism, such as an out-of-order processing circuitry, and a second execution mechanismsuch as an in-order processing circuitry. Switching control circuitry controls switching between which of the first execution circuitry and the second execution circuitry is active at a given time. Latency indicating signals indicative of the latency associated with a candidate switching operation to be performed are supplied to the switching control circuitry and used to control the switching operation. The control of the switching operation may be to accelerate the switching operation, prevent the switching operation, perform early architectural state data transfer or other possibilities.

Control of switching between executed mechanisms

A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode.

Growing community of inventors

Ann Arbor, MI, United States of America

Andrew Lukefahr