Altera Corporation

Intel Corporation

Groq, Inc.

Andrew Ling

Gordon Raymond Chiu

Davor Capalija

Utku Aydonat

Shigeki Tomishima

Chetan Chauhan

Tomasz Czajkowski

Nilesh N Shah

Andrei Mihai Hagiescu Miriste

Nahid Hassan

Jonathan Alexander Ross

Eriko Nurvitadhi

Deshanand Pratap Singh

Dennis Charles Abts

Deborah T Marr

John Stuart Freeman

Byron Sinclair

Shane O'Connell

Michael Bye

Alan Baker

Garrin Kimmell

Meghan Lele

Matthew Boyd

Jack Z Yinger

A system contains a network of processors arranged in a plurality of nodes. Each node comprises a respective plurality of processors connected via local links, and different nodes are connected via global links. The processors of the network communicate with each other to establish a global counter for the network, enabling deterministic communication between the processors of the network. A compiler is configured to explicitly schedule communication traffic across the global and local links of the network of processors based upon the deterministic links between the processors, which enable software-scheduled networking with explicit send or receive instructions executed by functional units of the processors at specific times, to establish a specific ordering of operations performed by the network of processors. In some embodiments, the processors of the network of processors are tensor streaming processors (TSPs).

Software-defined tensor streaming multiprocessor for large-scale machine learning

Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

Data processing near data storage

Matrix multiplication systolic array feed methods and related processing element (PE) microarchitectures for efficiently implementing systolic array generic matrix multiplier (SGEMM) in integrated circuits is provided. A systolic array architecture may include a processing element array, a column feeder array, and a row feeder array. A bandwidth of external memory may be reduced by a factor of reduction based on interleaving of the matrix data via a feeding pattern of the column feeder array and the row feeder array.

Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers

Examples herein relate to a solid state drive that includes a media, a processing system, and a media command arbiter configured to permit execution of a specific allocation of storage and compute commands based on a configuration, wherein the media command arbiter is to transfer commands to the media based on the configuration. The media can be locally connected to a compute engine processing system that is configurable to perform computations on data stored in the media. The configuration can indicate a number of compute commands and storage commands that are permitted to be performed over a period of time or media bandwidth allocated to compute commands and storage commands. The processing system can include an inference engine that performs one or more of: data pattern recognition, image recognition, augmented reality overlay applications, face recognition, object recognition, or voice recognition, language translation.

A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to perform convolution. A configuration of the CNN accelerator is modified to change filters implemented by the CNN accelerator and to change formatting of output data. The one or more processing elements are utilized to perform one of deconvolution and backpropagation convolution in response to the change in the filters and formatting of the output data.

Method and apparatus for performing different types of convolution operations with the same processing elements

Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

Channel sizing for inter-kernel communication

A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the CNN accelerator is modified to change a data flow between components on the CNN accelerator. The one or more processing elements is utilized to implement a fully connected layer in response to the change in the data flow.

Method and apparatus for implementing layers on a convolutional neural network accelerator

A method for implementing a convolutional neural network (CNN) accelerator on a target includes identifying characteristics and parameters for the CNN accelerator. Resources on the target are identified. A design for the CNN accelerator is generated in response to the characteristics and parameters of the CNN accelerator and the resources on the target.

Method and apparatus for designing and implementing a convolution neural net accelerator

Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.

Dot product based processing elements

Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Global variable implementation logic may be used to optimize implementation, on an integrated circuit, of functionality represented by high-level code including global variables. A compiler's intermediate representation is analyzed for one or more characteristics that may be used to determine one or more initialization parameters, one or more scope parameters, one or more implementation parameters, or any combination thereof of the functionality. An HDL is generated based upon the one or more initialization parameters, the one or more scope parameters, the one or more implementation parameters, or the any combination thereof.

Global variable optimization for integrated circuit applications

Devices and methods for filtering data include calculating intermediate input values from input elements using a transformation function. The transformation function is based at least in part on a size of the filter and a number of filter outputs. Intermediate filter values are calculated from filter elements of the filter using the transformation function. Each intermediate input value is multiplied with a respective intermediate filter value to form intermediate values. These intermediate values are combined with each other using the transformation function to determine one or more output values.

Fast filtering

A method for placing a system on a structured application specific integrated circuit (ASIC) using an electronic design automation tool is disclosed. A subregion that includes an illegal position in a placement solution is identified. All structured ASIC cells in the subregion are removed. Positions for all the structured ASIC cells that are legal are determined.

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Toronto, Canada

Andrew Ling