Altera Corporation

Andrew Leaver

Michael David Hutton

Sergey Yuryevich Shumarayev

Bruce B Pedersen

Rakesh H Patel

David Wolk Mendel

Wei-Jen Huang

Tony K Ngai

James G Schleicher

Stephen D Brown

David Karchmer

Terry Borer

Gabriel Quan

Victor Maruri

Jim Park

Peter J Kazarian

Vaughn Betz

Francis B Heile

Babette Van Antwerpen

Kevin Chan

Jason Govig

Swatiben Ruturaj Pathak

A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.

Method and apparatus for performing compilation using multiple design flows

M/A for performing incremental compilation using top-down and bottom-up design approaches

Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches

Circuits, methods, software, and apparatus that track the removal of, reasons for, and consequence of the removal of registers or other circuitry during the synthesis of electronic circuits. An exemplary embodiment of the present invention tracks the removal of registers and determines why the registers were removed. This information is then provided in an efficient manner for design debugging purposes.

Tracing and reporting registers removed during synthesis

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Interconnection and input/output resources for programmable logic integrated circuit devices

A method for designing a system on a target device includes merging a post-fit netlist for a first partition of the system from a set-up compilation with a post-synthesis netlist for a second partition of the system from an incremental compilation to form a combined netlist. Fitting is performed on the combined netlist.

Method and apparatus for performing incremental compilation

A method and mechanism for mapping heterogeneous logic elements in a portion of electronic design compilation for a programmable integrated circuit is disclosed. Specifically, the invention provides a method to perform the technology mapping of heterogeneous logic elements in a programmable logic device such as selectively choosing the best combination of product term logic elements and look up table logic elements.

Mapping heterogeneous logic elements in a programmable logic device

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Los Altos, CA, United States of America

Andrew Leaver