Hewlett-Packard Development Company, L.p.

Andrew L VanBrocklin

Frederick A Perner

James Michael Gardner

Warren Bruce Jackson

Peter James Fricke

Kenneth Kay Smith

Kenneth James Eldredge

Brett E Dahlgren

Stephan R Clark

A color detector includes a light source, a first filter, and a first photodetector. The light source generates light within a spectrum of wavelengths. The first filter is in optical communication with the light source and is configured to pass light within a first predetermined spectrum of wavelengths. The first photodetector is in optical communication with the first filter and is configured to output a first color signal if light passes through the first filter. The photodetector has an area configured to equalize the first color signal and maximize a signal-to-noise ratio of the first color signal.

Color detector having area scaled photodetectors

A resistive cross point memory cell array comprising a plurality of word lines, a plurality of bit lines, a plurality of cross points formed by the word lines and the bit lines, and a plurality of memory cells, each of the memory cells being located at a different one of the cross points, wherein a first bit line comprises a distributed series diode along an entire length of the bit line such that each of the associated memory cells located along the first bit line is coupled between the distributed series diode and an associated word line.

Data storage device and method of forming the same

Embodiments of the present invention provide a memory device. In one embodiment, the memory device comprises an array of memory cells configured to provide resistive states, a read circuit configured to sense the resistive states and a resistor. The resistor is configured to provide a resistance to the read circuit that is configured to select the resistor and sense the resistance to test the read circuit.

Memory device

A memory array according to a particular embodiment of the invention includes a substrate, a plurality of first select-lines disposed in a plurality of planes generally parallel to the substrate, a plurality of second select-lines formed in pillars disposed generally orthogonal to the substrate, a plurality of memory cells coupled to the first select-lines and the second select-lines, and a current path connection providing a continuous current path through a selected plurality of the pillars to heat the selected pillars and cause at least one memory cell associated with the selected pillars to be reset.

Memory array with continuous current path through multiple lines

Systems and methods for storing data are provided. A representative system for storing data includes a magnetic random access memory (MRAM) device having a plurality of memory cells. Each memory cell includes a magnetic tunnel junction and a non-magnetic tunnel junction that are connected in series. The magnetic tunnel junction stores a bit value corresponding to a logic high (1) or a logic low (0). The non-magnetic tunnel junction provides little resistance when the memory cell is being read, and a substantially high resistance when the memory cell is not being read. As a result, a negligible level of parasitic current leaks through memory cells that are not being read.

Magnetic random access memory with reduced parasitic currents

A memory cell includes a heating component that is connected to a voltage-breakdown component. The heating component is configured to accelerate the break-down of a voltage-breakdown component. Memory structures and methods for making them are also disclosed.

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Corvallis, OR, United States of America

Andrew L VanBrocklin