Cypress Semiconductor Corporation

Andrew L Hawkins

Pidugu L Narayana

Stefan P Sywyk

Jeffery Scott Hunt

George M Ansel

Richard K Chou

Roland T Knaack

Ajay Srikrishna

Muthukumar Nagarajan

Daniel Eric Cress

Satish C Saripella

David Robert Lindley

Junfei Fan

Ping Wu

Jeffrey W Gossett

Michael D Carlson

Sanjay Sunder

William G Baker

Raymond E Bloker

Derrick J Savage

James E Kelly

David A Lindley

A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.

Address counter test mode for memory device

In a single ended simplex dual port memory cell, one port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Single ended simplex dual port memory cell

The present invention provides a circuit for writing a particular sized data word from a common input to a number of individual memory cells in a memory array and reading a particular sized data word from the individual memory cells to a common output. The size of the word written to the memory cells can be larger, smaller or the same as the size of the word read from the memory array. The present invention uses a multi-bit write counter to distribute a write timing signal to a number of multiplexer blocks and a multi-bit read counter to distribute a read timing signal to a number of sense amplifier blocks. Each of the multiplexer blocks receives both a data input signal from the common input and the write timing signal continuously when the circuit is in operation. Each of the sense amplifier blocks receives data from the memory array and a read timing signal at all times. When a particular read timing signal is present at a sense amplifier, the output signal containing a fixed width data word is received from one or more of the corresponding memory arrays and is presented to the common output. The present invention reduces the number of internal signal lines necessary to implement the control function and allows for easy modification to both read and write multiple width words to and from the memory array.

Clocking scheme for independently reading and writing multiple width words from a memory array

A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

A method of reading the contents of a dual port memory cell which has a Beta Ratio less than 1.5 is described. A wordline is associated with a selected port of the memory cell. The wordline is coupled to a gate device of the memory cell for controlling communication between the memory cell and a bitline. The gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage. The second conductance is less than the first conductance. A port of the cell is selected by applying a select voltage to the associated wordline. The select voltage is approximately the same as the second wordline voltage. The cell contents are then retrieved from the bitline.

Single ended dual port memory cell

An efficient design to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation. From the sum and carry outputs of the first stage bitwise addition, bits with equal weights are united and the overall carry out of this addition is generated very efficiency. The overall carry represents the external almost empty or almost full flag.

Circuit for generating almost full and almost empty flags in response to

A circuit that may be used as a memory cell that may be capable of a differential write and a single ended read. The circuit generally comprises a memory storage element having a write bitline, a complement write bitline and a read bitline. One or more first gates may be configured to pass data on the write bitline and the inverted write bitline during a write operation. The write operation may occur in response to a write control signal. A second gate may be configured to pass data on from the storage element to the read bitline in response to read control signal. As a result, the circuit may be written by both the write bitline and the complement write bitline and may be read by the read bitline.

Memory cell

A circuit and method for staggering a bitline precharge between particular sections of a memory array. The present invention may be implemented in memories having increasing depths to reduce unacceptably high precharge current requirements associated with high bitline loads. Since the particular memory sections of the memory array are turned on independently, the peak current necessary to charge the particular bitlines is limited. The present invention may be implemented in logic and may therefore be less sensitive to process and temperature variations.

Staggered bitline precharge scheme

A state machine for generating a flag that represents the fullness of a FIFO buffer is disclosed. The present invention generates a set of next state variables that are derived generally from a combination of three previous state variables and three additional inputs representing an internally generated look-ahead flag, an external write clock and an external read clock. The next state variables are derived specifically from a product of the previous state variables and complement signals of the previous state variables. The full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal and a look-ahead decoded internal full flag signal. An empty flag can be generated by switching the read and write clock inputs and changing the look-ahead decoded internal full flag to a look-ahead decoded internal empty flag. All of these features are realized without requiring any counters, adders or decoders in the speed path of the state machine.

State machine design for generating empty and full flags in an

A single ended dual port memory cell is described. A bit of data received from one of the first and second ports can be stored. Each of the first and second ports can simultaneously detect the stored bit. A method of reading the contents of a dual port memory cell which has a Beta Ratio less than 1.5 is also described. A wordline is associated with a selected port of the memory cell. The wordline is coupled to a gate device of the memory cell for controlling communication between the memory cell and a bitline. The gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage. The second conductance is less than the first conductance. A port of the cell is selected by applying a select voltage to the associated wordline. The select voltage is approximately the same as the second wordline voltage. The cell contents are then retrieved from the bitline.

Single ended simpler dual port memory cell

The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Half-full flag generator for synchronous FIFOs

A state machine design which can be used to realize extremely short flag generation delays. The present invention also realizes the benefit of having an extremely high MTBF. The present invention generates a set of next state variables that are generated from a combination of three previous state variables and three additional inputs representing a logical 'OR' of a read half-full and write half-full flag WRH, an external write clock input, and an external read clock input. The next state variables are derived from a product of the previous state variables, a complement signal of the previous state variables, and the signal WRH. The half-full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal.

State machine design for generating half-full and half-empty flags in an

The present invention provides an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

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Starkville, MS, United States of America

Andrew L Hawkins