Texas Instruments Corporation

Other

Oracle America, Inc.

Plessey Overseas Limited

Gec Plessey Telecommunications Limited

Andrew Keith Joy

Richard Ward

Hae-Chang Lee

Arnold Robert Feldman

Robert Simpson

Richard D Simpson

Iain Craig Robertson

Nirmal Chindhu Warke

Drew George Doblar

Dawei Huang

Michael Stephen Harwood

Giuseppe Surace

Deqiang Song

Andrew J Pickering

Zuxu Qin

Derek Colman

Andrew James Pickering

John S Arnold

William Franklin Leven

Dong Joon Yoon

Michael David Jager

Waseem Ahmad

Tom Leslie

Osman Javed

Daniel J Beckman

Raymond E Oakley

Sue Simpson

Simon Dennis Forey

Peter H Saul

A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h=h+h; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.

Clock data recovery system

A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at a second post cursor; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.

A feedback module is defined to receive as input a set of data sample signals and a set of reference sample signals. Each of the data and reference sample signals is generated by sampling a differential signal having been transmitted through a FIR filter. The feedback module is defined to operate a respective post cursor counter for each post cursor of the FIR filter and update the post cursor counters based on the received sets of data and reference sample signals. Also, the feedback module is defined to generate a tap weight adjustment signal for a given tap weight of the FIR filter when a magnitude of a post cursor counter corresponding to the given tap weight is greater than or equal to a threshold value. An adaptation module is defined to adapt a reference voltage used to generate the reference sample signals to a condition of the differential signal.

Real-time optimization of TX FIR filter for high-speed data communication

There is provided a power supply monitor circuit comprising a positive supply monitoring input, a negative supply monitoring input, and a voltage divider connected between the positive and negative supply monitoring inputs and having an intermediate node providing a potential intermediate those on the positive and negative supply monitoring inputs. A sampling circuit is connected to sample the potential at each of the positive supply input the negative supply input and the intermediate node. Also provided is a method of monitoring noise on a power supply whereby phase information from those samples is derived about the noise signals at the two said points.

Power supply monitor

In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronized with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronized with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.

Synchronising circuit

A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Data transmission

A differential data transmission system that transmits encoded data symbols as differential signals. A signal for transmitting symbols on a set of at least three parallel channels, each channel having a first terminal, Pto PN, and each channel having a second terminal connected to a common node Z. The signal comprising for each symbol an active signal on two of those channels and an inactive signal on the remaining channel or channels, the symbols being distinguishable by which two of the channels have the active signals.

Systems for data transmission

An asynchronous time division multiplex switching arrangement comprises a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the packets of data to parallel form. A random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output.

Asynchronous time division switching arrangement and a method of

A power supply for an integrated circuit chip, including supply regulation circuitry coupled between on-chip circuitry and a power supply connection, the supply regulation circuitry including a transistor having a diode coupled to the control electrode of the transistor, the diode having a relatively large diode junction area, and a resistor coupled in series with the main current path of the transistor having a relatively small or no diode junction area, whereby when the chip is subject to irradiation the diode means increases the conductivity of the main current path so that an increased voltage appears across the resistor thereby to reduce the supply voltage to the on-chip circuitry.

Radiation hardened power supplies for integrated circuits

Growing community of inventors

Northampton, United Kingdom

Andrew Keith Joy