Alpine Microsystems, Inc.

Andrew K Wiggin

George E Avery

Sammy K Brown

Martin P Goetz

Sam Beal

Tom L Todd

John J Zasio

Samuel W Beal

Allan Calamoneri

A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system while reducing contact degradation due to stress that results from differences in the coefficients of thermal expansion of the various components during thermal cycling

Method for mounting an integrated circuit having reduced thermal stresses between a bond pad and a metallic contact

A plurality of integrated circuits are efficiently interconnected to improve the electrical performance of the overall system. This is accomplished by providing high speed, high density, system level interconnect, including interchip routing lines, on the integrated circuit devices, thereby reducing the routing complexity of the substrate or board. The devices are mounted directly on the board. An integrated circuit device comprises an integrated circuit region including integrated circuit elements. An interconnect layer includes an insulative material, a plurality of conductive traces, and a plurality of conductive bond pads arranged in first and second subsets. A first subgroup of the conductive traces are connected to the integrated circuit elements in the integrated circuit region and are connected to the first subset of conductive bond pads. A second subgroup of the conductive traces are electrically insulated from the integrated circuit elements and are electrically insulated from the first subgroup of the conductive traces to form a pass through. The second subgroup of the conductive traces are connected to the second subset of conductive bond pads.

Integrated circuits packaging system and method

A method and a system for wafer level burn-in testing of a circuit featuring a flip-jumper to permit selectively connecting signals to the interconnect sites on the wafer that are in constant electrical communication with the circuit.

Wafer-level burn-in

A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system while reducing contact degradation due to stress that results from differences in the coefficients of thermal expansion of the various components during thermal cycling.

System and method for packaging integrated circuits

A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system. In one embodiment of the system of the present invention, a plurality of carriers corresponds to a plurality of ICs, and a board has a plurality of board regions for receiving the plurality of ICs and are arranged so as to be attached to a backplane forming a vertical stack of boards.

Three dimensional mounting assembly for integrated circuits

A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system. In one embodiment of the system of the present invention, a plurality of carriers corresponds to a plurality of ICs, and a board has a plurality of board regions for receiving the plurality of ICs. In one embodiment of the method of the present invention, a carrier is provided for each IC in a complex IC. A board having openings is provided, and the ICs are fitted into the board openings with the carriers mounted thereto.

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San Carlos, CA, United States of America

Andrew K Wiggin