Quicklogic Corporation

Other

Monolithic Memories, Inc.

Advanced Micro Devices Corporation

Advance Micro Devices, Inc.

Advanced Micro Device, Inc.

Andrew K Chan

John M Birkner

Hua-Thye Chua

James M Apland

Mammen Thomas

Ralph G Whitten

Richard L Bechtel

Kathryn E Gordon

Albert L Chan

Vincent K Win

Mark E Fitzpatrick

David D Eaton

Cyrus Y Tsui

Ket-Chong Yap

Qinggang Zhou

Clyde H Nagakura

Hua T Chua

Kevin K Yee

Sheng-Fu Wu

Richard J Wong

Thomas Chan

William D Cox

Brian D Small

Paige A Kolze

Robert Chipin Fu

Senani Gunaratna

Drazen Borkovic

Sing Y Wong

Behzad Nouban

Po Weng Chiu

Mukesh T Lulla

Gary Gouldsberry

Cuong O Trinh

James A Apland

Neal A Palmer

Michael W Dini

Panawalge S N Gunaratna

Vincent K Zaw Win

SunilKumar G Mudunuri

Amarpreet S Chawla

Harry J Raftopoulos

Charles C Tralka

Roger Ang

Zahid Ansari

Bob Bosnyak

Atul Ahuja

Danesh M Tavana

E Thomas Hart

Robert Fu

A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Deinterlacer using low angle or high angle spatial interpolation

A display processor integrated circuit (for example, for a television or for a digital camera) includes a display processor portion and an on-chip programmable logic portion. The on-chip programmable logic portion can be configured or programmed to implement custom video and/or image enhancement functions. Accordingly, an individual television or camera manufacturer can have his/her own custom enhancement function incorporated into the display processor integrated circuit by having the programmable logic portion configured or programmed appropriately. In one embodiment, the programming of the programmable logic portion involves changing just one mask, thereby reducing the cost, complexity and time associated with implementing the custom video/image enhancement function.

Display processor integrated circuit with on-chip programmable logic for implementing custom enhancement functions

A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function. I/O terminals that were used to couple to the external FPGA during system development are usable during normal operation to provide system board access to circuitry within the mask-programmable portion.

ASIC having dense mask-programmable portion and related system development method

Deinterlacer using block-based motion detection

Deinterlacer using both low angle and high angle spatial interpolation

A RAM device, such as the type embedded in a programmable logic device, is configurable to alter the depth of the addressable elements and the width of the number of data bits received or produced by the RAM device. The RAM device includes a number of address ports for receiving the read and/or write address signals, but the RAM device may be configured such that the depth requires fewer address signals then there are address ports. Likewise, the RAM device includes a number of input and output data ports for receiving and producing the data bits, but the width of the RAM device may be configured such that the number of data bits actually received or produced are less than the number of data ports. The depth and the width of the RAM device are configured together so that the depth is increased when the width is decreased and vice versa. This permits a number of appropriately configured RAM devices to be combined to produce a deep and wide RAM circuit without requiring the use of additional logic blocks, such as buffers, inverters, and multiplexors that reduce the speed of the circuit.

RAM with configurable depth and width

A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors. The input/output terminals around the periphery and in the interface between the programmable circuit and dedicated device are tested using JTAG registers. The path of the test signal through the JTAG registers is selectable to pass around the periphery of both the programmable and dedicated devices or through the interface and around the periphery of only one of the programmable and dedicated devices.

Programmable antifuse interfacing a programmable logic and a dedicated device

In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.

Serializer/deserializer embedded in a programmable device

A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i.e., it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bits and restricts access to embedded portion based on the configuration.

Programmable device with an embedded portion for receiving a standard circuit design

A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

Architecture for field programmable gate array

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Method for fabrication of programmable interconnect structure

A programmable integrated circuit (see FIG. 13) includes a plurality of routing resources including collinearly extending routing wire segments and a test circuit for testing the integrity of the routing wire segments. The routing resource structures include a plurality of unprogrammed antifuses disposed between routing wire segments and a plurality of transistors disposed electrically in parallel with a corresponding respective one of the antifuses. The test circuit has a common node that may be coupled to a selected one of the routing resource structures for testing. In test mode, the test circuit detects whether a current flows through the selected routing resource structure and in response provides either a digital low value or a digital high value on an output node.

Programmable integrated circuit having a test circuit for testing the

A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

Power-up circuit for field programmable gate arrays

A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.

Precharge circuitry in RAM circuit

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Programmable application specific integrated circuit and logic cell

Growing community of inventors

Palo Alto, CA, United States of America

Andrew K Chan