Analog Devices,inc.

Linear Technology Corporation

Analog Devices International Unlimited Company

Linear Technology Holding LLC

Andrew Joseph Thomas

Joseph L Sousa

Jesper Steensgaard-Madsen

Roberto Sergio Matteo Maurino

Micah Galletta O'Halloran

Christopher Peter Hurrell

Alfio Zanchi

David M Thomas

Venkata Aruna Srikanth Nittala

Bhargav R Vyas

Alex Robert Sloboda

An analog-to-digital converter (ADC) system, such as a subranging ADC, including a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, buffer circuits can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.

Subranging ADC buffer cascade

Circuit techniques for providing base-current cancellation of a bipolar junction transistor (BJT) differential pair that compensate for tail current noise and differential voltage transients without penalizing supply headroom.

Low-headroom dynamic base current cancellation techniques

Systems and techniques for Digital-to-Analog Converter (DAC) gain correction are described herein. A digital-to-analog converter (DAC) circuit can include a switch bridge circuit having a first leg and a second leg that define respective mutually exclusive first and second DAC signal paths. The DAC circuit can further include a first compensation circuit configured to provide a first compensation current to the first leg of the switch bridge to compensate for a current defect caused by a voltage drop across a portion of the first DAC signal path. The DAC circuit can also include a second compensation circuit configured to provide a second compensation current to a second leg of the switch bridge to compensate for a voltage drop across a portion of the second DAC signal path. The DAC circuit can be included in a larger circuit such as a continuous time sigma delta (CTSD) analog-to-digital converter (ADC).

Resistor DAC gain correction

A measurement circuit comprises an input terminal to receive a current signal, a first circuit branch coupled to the first terminal and including one or more circuit elements to receive a portion of the current signal, a second circuit branch coupled to the first terminal and including one or more additional circuit elements to receive another portion of the current signal, a nonlinear circuit element coupling the first circuit branch to the second circuit branch, and a quantization circuit configured to produce an input current measurement of current in the first and second circuit branches, and to include current in the second circuit branch in the input current measurement according to a magnitude of the input current signal.

Precision dynamic range expansion for current measurement

A signal conditioning circuit to reduce detrimental effects of analog circuit elements. The techniques described herein provide a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, a buffer can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.

Buffer cascade

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

Analog-to-digital converter with auto-zeroing residue amplification circuit

Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

Low-noise, high-accuracy single-ended input stage for continuous-time sigma delta (CTSD) analog-to-digital converter (ADC)

A circuit having a capacitance driver circuit can allow for reduction of thermal noise to an application circuit. An output of the capacitance driver circuit can drive a capacitor for use by the application circuit coupled to the capacitor at the output of the capacitance driver circuit. The capacitance driver circuit can be structured to operate over a bandwidth of interest. With an input signal, received at the capacitance driver circuit, associated with a target voltage, an output voltage can be provided at the output of the capacitance driver circuit as a bandlimited filtered voltage value of the target voltage, where a root-mean-square voltage deviation of the output voltage from the target voltage, due to thermal noise, is less than a square root of (kT/C). The term k is Boltzmann's constant, T is Kelvin temperature of the capacitance driver circuit, and C is the capacitance of the driven capacitor.

Noise reducing capacitance driver

A measurement circuit comprises an electronic circuit, multiple measurement channels, and a combining circuit. The electronic circuit includes a first terminal, a second terminal, and a non-resistive circuit element. Each of the multiple measurement channels includes a differential input connected to the electronic circuit. The differential inputs of the multiple measurement channels are connected in series and include a differential input coupled to the non-resistive circuit element. One input of a differential input of a first measurement channel of the multiple measurement channels is connected to the first terminal of the electronic circuit and one input of a differential input of a second measurement channel of the multiple measurement channels is connected to the second terminal of the electronic circuit. The combining circuit receives multiple outputs from the multiple measurement channels and produce a composite output signal.

Electrical signal measurement using subdivision

Techniques to provide automatic-gain ranging for high dynamic range by including a separate S/H capacitor, segmenting the S/H capacitor into a plurality of capacitors, and determining the number of segments to use for a sample. In this manner, the size of the S/H capacitor can be changed (by adjusting the number of capacitors), which can change the amount of input voltage that produces an amount of charge. Using these techniques, the full-scale input range for a sample of the analog input signal can be adjusted automatically based on the magnitude of the sample, which can provide better resolution and/or better noise performance for that particular sample then would otherwise be possible.

High dynamic range analog-to-digital converter

Sample-and-hold (S/H) circuitry operating in track and hold phases and having a first S/H circuit with a first hold capacitor at which a first voltage value is maintained in the hold phase, and a dielectric absorption (DA)-suppressing circuit connectable to the first hold capacitor for operating the S/H circuitry in an additional phase after completing the hold phase and before entering the track phase. The DA-suppressing circuit is configured to supply the first hold capacitor, during an operation in the additional phase, with a second voltage value that is negatively correlated with the first voltage value.

Suppressing dielectric absorption effects in sample-and-hold systems

Circuits and methods for maintaining a substantially constant input and output current for a charge pump circuit are provided which reduce current variation during switching intervals. The charge pump circuitry of the present invention maintains a current flow path from a current source to the charge pump output which minimizes or eliminates spikes normally associated with the switching intervals.

Charge pump with reduced current variation

A system is configured and a method is provided for receiving an input ratio represented by a first input signal and a second input signal, and producing an output ratio represented by a first output signal and a second output signal. The system is constructed and the method is provided for alternately operating in at least two time periods, wherein in one time period the first input signal, a low accuracy amplifier, and the first output signal are selectively coupled, and in another time period the input signal, the low accuracy amplifier, a high accuracy attenuator, and the second output signal are selectively coupled so as to maintain the output ratio proportional to the input ratio.

Time-multiplexed residue amplifier

A circuit includes a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference signal and (2) as a function of a digital input signal. The converter comprises a plurality of non-trivially complex admittances configured so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference signal and an output terminal. The method comprises selectively switching non-trivially complex admittances as a function of the digital signal between a reference terminal and an output terminal.

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Arlington, MA, United States of America

Andrew Joseph Thomas