Arm Limited

Samsung Electronics Co., Ltd.

Andrew Joseph Rushing

Tessil Thomas

Kevin Michael Lepak

Ali Ghassan Saidi

Michael Filippo

Andreas Hansson

Kshitij Sudan

An apparatus and method are provided for processing flush requests within a packet network. The apparatus comprises a requester device within the packet network arranged to receive a flush request generated by a remote agent requesting that one or more data items be flushed to a point of persistence. The requester device translates the flush request into a packet-based flush command conforming to a packet protocol of the packet network. A completer device within the packet network that is coupled to a persistence domain incorporating the point of persistence is arranged to detect receipt of the packet-based flush command, and then trigger a flush operation within the persistence domain to flush the one or more data items to the point of persistence. This provides a fast, hardware-based, mechanism for performing a flush operation within a persistence domain without needing to trigger software in the persistence domain to handle the flush to the point of persistence.

Apparatus and method for processing flush requests within a packet network

A data processing apparatus is provided that comprises volatile storage circuitry to store data while power is provided. Persistent storage circuitry stores data in the absence of power and transfer circuitry transfers data from the volatile storage circuitry to the persistent storage circuitry. The transfer circuitry is adapted to transfer the data from the volatile storage circuitry to the persistent storage circuitry in response to a primary power supply becoming unavailable to the volatile storage circuitry. The transfer circuitry is adapted to transfer a subset of the data from the volatile storage circuitry to the persistent storage circuitry in response to an explicit request comprising an indication of the subset of the data.

Persistent memory cleaning

According to one general aspect, a method may include receiving a request, from a non-central processor device that is configured to perform a direct memory access, to write data within a memory system at a memory address. The method may also include determining if a cache tag hit is generated, based upon the memory address, by a caching tier of the memory system that is closer, latency-wise, to a central processor than a coherent memory interconnect. The method may further include if the caching tier generated the cache tag hit, injecting the data into the caching tier.

Opportunistic cache injection of data into lower latency levels of the cache hierarchy

Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.

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Austin, TX, United States of America

Andrew Joseph Rushing