Dialog Semiconductor Gmbh

Dialog Semiconductor (uk) Limited

Dialog Semiconductor B.v.

Andrew John Myles

Justin Richardson

Andrew Terry

Mairead Kelly

A voltage selection circuit for selecting a voltage from a plurality of input voltages comprising a plurality of diodes, each diode having a first terminal coupled to one of the input voltages, and a current sensor configured to sense a current flow through each diode, wherein the selected voltage is dependent on the sensed current flow. In operation, the circuit functions as a comparator to detect the maximum among the input voltages. The comparator decision is used to close one or more of the power switches to ensure that the load is powered from the highest input voltage.

Voltage selection circuit

A fully differential amplifier performs common-mode voltage control while having reduced sensitivity to random offsets and mismatches and improved common-mode control loop bandwidth. The amplifier disclosed comprises an additional common-mode control sub-amplifier, which senses common-mode voltage of the fully differential main amplifier at nodes within the continuous-time signal path feedback network, compares the common-mode voltage sensed with a reference voltage, and regulates depending on the result of the comparison the output common-mode voltage via the existing continuous signal path feedback network. Furthermore the internal common-mode control can be implemented in such a manner as to provide a feed-forward transconductance function in addition to common-mode control if desired. Moreover it is possible to use feedback from other amplifier stages in an amplifier chain to implement common-mode feedback.

Amplifier common-mode control method

A capacitance reduction circuit retains a conversion digital code of a previous sampling of an input signal of a delta-sigma modulated ADC and compares a set of least significant data bits and most significant bits of the conversion digital code to a least significant and a most significant boundary codes. When the least significant bits of the conversion digital code are less than or equal to the least significant boundary code or when the most significant bits of the conversion digital code are greater than or equal to the most significant boundary code, the capacitance reduction circuitry generates a capacitance reduction enable/disable code applied to multiple summation-quantization circuits to enable or disable groups of the multiple summation-quantization circuits bits to reduce capacitive loading of the outputs of delta-sigma modulator and an input signal to improve the total harmonic distortion and noise.

Flash converter capacitance reduction method

The present disclosure relates to methods and circuits to achieve ground centered charge-pumps generating output voltages of +/&#x2212;VDD/2 or +/&#x2212;VDD/3 while achieving high efficiency of power conversion and minimized output impedances. Key points of the disclosure are minimizing number of switching states, reducing the time required for transition through all switching states, maintain constant flying capacitor voltages in all switching states, and, ideally, configuring the size of the flying capacitors large enough to provide the required load charge of each switching state without voltage change of the flying capacitors.

Divide by 2 and 3 charge pump methods

This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating to the more advanced technology node of next generation. The invention adopts a novel preferable symmetrical 2T-string NOR flash cell. Each NAND or NAND like cell of this 2T-string NOR cell is to store 2 bits and is preferable to be made of N-channel device. The cell is preferable to use Fowler-Nordheim Tunneling scheme for both erase and program operations- The invention is to provide a novel 2T-string NOR flash cell structure made of N-channel device offering most flexible erase sizes in unit of byte, page, sector, block and chip with the least program and erase disturbances.

High gain amplifier method using low-valued resistances

Systems and methods for providing a fully differential amplifier performing common-mode voltage control having reduced area and power requirements are disclosed. The amplifier disclosed comprises an additional input stage at the amplifier input which senses the common mode voltage of the amplifier's inputs and applies internal feedback control to adjust the output common-mode voltage until the input common-mode voltage matches a target voltage and thereby indirectly set the output common-mode voltage. Furthermore the internal common-mode control can be implemented in such a manner as to provide a feed-forward transconductance function in addition to common-mode control if desired. Moreover it is possible to use feedback from other amplifier stages in an amplifier chain to implement common-mode feedback.

Amplifier common-mode control methods

Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

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Edinburgh, United Kingdom

Andrew John Myles