Arm Limited

Andrew John Merritt

Alex Beharrell

Raghavendra Adiga Bandimutt

Michael John Williams

Peter Logan Harrod

Simon Anthony Segars

Saqib Rashid

There is provided an apparatus that includes a first port that receives first data of a first type from a first storage circuit. A second port receives second data of a second type from a second storage circuit having a lower worst case latency in hardware than the first storage circuit. A third port receives access requests for the first data and the second data from a processing circuit. When one of the access requests is received for the first data, it is forwarded to the first storage circuit and when the one of the access requests is received for the second data, it is forwarded to the second storage circuit. A shared storage circuit stores the first data and the second data and has a storage capacity.

Storing data from low latency storage

Apparatuses and methods of operating apparatus are disclosed. A processing element performs data processing operations with respect to data items stored in data storage. In a first mode the processing element references the data items using physical addresses and in a second mode the processing element references the data items using virtual addresses. A data access request handling unit receives data access requests issued by the processing element and cache stores cache lines of temporary copies of the data items retrieved from the data storage, wherein a cache line in which a data item is stored in the cache is selected in dependence on an address index portion. The data access request handling unit is responsive to a data access request for the data item from the processing element in the second mode to determine an index matching condition to be true when the address index portion of the physical address of the data item matches the address index portion of the virtual address of the data item and, when the index matching condition is false, to prevent allocation of the data item into the cache.

Cache operation in an apparatus supporting both physical and virtual address mapping

A processing system is described including a processor unit and a memory Diagnostic hardware within the processing system includes a shadow PC register that stores a shadow program counter value following the true program counter value held within a program counter register of the processor unit The diagnostic hardware is responsive to a program counter request signal from an external diagnostic system to transfer a program counter value into a scan chain from where it can be returned to the diagnostic system The operation of the processor unit is independent of any of the diagnostic operations and so true real time operation of the system may be observed and de-bugged.

Asynchronously accessing the program counter values of a data processing system by applying an independent clock on the latching and scan-chain circuits

The present invention provides a debugger interface unit for a data processing apparatus, comprising a control register having a number of fields, each field corresponding to a particular exception routine, and each field being settable to indicate that the debugger wishes to identify an access to the corresponding exception routine. Further, an exception routine catch logic is provided to receive a first signal when a processor core within the data processing apparatus issues an instruction fetch command for an exception routine, and to determine from an instruction address issued with the instruction fetch command which exception routine is being fetched. In addition, the catch logic is arranged to reference the field of the control register corresponding to the determined exception routine to determine if that field has been set, and if the field has been set, to output a breakpoint signal to the processor core. The above approach provides a particularly efficient technique for identifying accesses to exception routines when debugging software, such identification being independent of the base address of the exception routines.

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Cambridge, United Kingdom

Andrew John Merritt