Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Andrew John Blanksby

Ba-Zhong Shen

Jason A Trachewsky

Alvin Lai Lin

Matthias Korb

Alvin Lin

Ron Porat

Arya Behzad

Joonsuk Kim

Mohyee Mikhemar

Dignus-Jan Moelker

Vinko Erceg

Erich Franz Haratsch

David Garrett

Jun Zheng

Tirdad Sowlati

Wei-Hong Chen

Sudharshan Srinivasan

Marc J Loinaz

Christopher John Howland

Ahmed Sayed

An system includes a port to receive a number of bits at a first frequency. One or more cells generate a signal for a channel with a channel frequency that is N times greater than the first frequency. The cells transmit at a second frequency that is M times greater than the first frequency but is smaller than the channel frequency. Interface links are coupled between a portion of the input bits of the port and the one or more cells and the portion of the input bits is encoded by thermometer coded T bits such that each one of the T bits is encoded by M repeated parallel bits having a value of a respective T bit. Each interface link includes M interface lines between each T bit and each first cell, and M is smaller than N to reduce the number of interface lines for the T bits.

Hybrid rate interface to reduce power consumption and area in high-speed DACs and digital transmitters

A transmitter includes a first digital-to-analog converter (DAC) circuit consisting of a first set of unary cells to mix a first set of digital input data with a first clock signal. A second DAC circuit includes a second set of unary cells to mix a second set of digital input data with a second clock signal. A third circuit provides signals to the first DAC circuit and the second DAC circuit to implement an assignment scheme to assign either an in-phase (I) component or a quadrature (Q) component to the first set of unary cells and the second set of unary cells. Based on the assignment scheme, the first set of digital input data include I-data and Q-data, and the second set of digital input data include I-data and Q-data.

Dynamic assignment with phase-preserving clipping technique for digital transmitters and power amplifiers

A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, a device encodes information using a low density parity check (LDPC) code to generate an LDPC coded signal and transmits the LDPC coded signal to another communication device. in other examples, a device receives an LDPC coded signal from another communication device and decodes the LDPC coded signal using an LDPC matrix. The LDPC matrix includes a left hand side matrix and a right hand side matrix (e.g., having CSI (Cyclic Shifted Identity) sub-matrices on a main diagonal and another diagonal adjacently located to the main diagonal).

Low density parity check (LDPC) codes for communication devices and systems

Various aspects of systems for generating parity bits for encoding based on a portion of a generator matrix are disclosed. In one aspect, a generator matrix includes a sub-block including a first set of elements circularly shifted from an identity matrix by a first amount, and a second set of elements circularly shifted from the identity matrix by a second amount. Bit permutation circuitry generates first bits according to input bits and the first amount. Each of the first bits is provided as input to a corresponding XOR device of XOR devices. Each of a set of storage registers stores an output of the corresponding XOR device. The bit permutation circuitry generates second bits according to the input bits and the second amount. The XOR devices perform bit-wise XOR operations on the stored outputs and the generated second bits, to provide a portion of the parity bits.

Direct parity encoder

Methods, systems, and apparatuses are described for providing device(s) with additional processing time to process a packet received wirelessly while still meeting the legacy SIFS time constraint. The additional processing time may be achieved by adding, by a device transmitting the packet, padding and/or a packet extension to the last symbol of the packet. The additional processing time provided to the device(s) advantageously reduces the amount of extra hardware that would normally be added to meet the SIFS time constraint. The amount of padding and/or packet extension to be added to the last symbol is balanced to minimize the complexity of the device(s) against the reduction in system efficiency incurred by the device(s).

Packet extension for wireless communication

Methods, systems, and apparatuses for opportunistic data transfer (ODT) are provided. ODT improves network coverage, reliability and/or efficiency by permitting data transfer consumers and network access providers to take advantage of communication opportunities that may be mutually beneficial. Fixed and mobile, personal or business, wired or wireless devices, may participate as ODT network operators, providers and/or consumers. ODT participants may be motivated to participate, for example, to reduce battery consumption and improve network coverage, reduce network congestion and interference. A phone, for example, may be enabled to send data to an Internet destination by ODT in lieu of a cellular network in particular circumstances, such as cellular network unavailability, with less costly data transfer and/or less battery power consumption. ODTs may be ad hoc or preauthorized and may be tracked, accounted, and compensated for, such as according to ODT service terms selected by each provider.

Opportunistic data transfer

A communication device or device includes a processor that generates and interprets signals that are transmitted and received via a communication interface. The processor receives an LDPC coded signal, via the communication interface, that is generated by puncturing at least one parity bit from another LDPC coded signal that is generated based on an LDPC code characterized by a first LDPC matrix. The processor operates on the first LDPC matrix to generate a second LDPC matrix by excluding at least one column and at least one row from the first LDPC matrix. The number of columns and rows excluded from the first LDPC matrix is based on the number of bits punctured from the other LDPC coded signal to generate the LDPC coded signal. The processor then decodes the LDPC coded signal using the second LDPC matrix to make estimates of information bits encoded within the LDPC coded signal.

Puncture-aware low density parity check (LDPC) decoding

Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows.

Selective merge and partial reuse LDPC (low density parity check) code construction for limited number of layers belief propagation (BP) decoding

Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (&#x3b3;) values and check edge message (&#x3bb;) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.

Accumulating LDPC (low density parity check) decoder

Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system.

Communication device architecture for in-place constructed LDPC (low density parity check) code

Modulation code set (MCS) and LDPC (Low Density Parity Check) coding within multiple user, multiple access, and/or MIMO wireless communications. Selective operation in accordance with different operational modes is performed. Operation within a first mode may correspond to that which is in full compliance with a given protocol, standard, and/or recommended practice, while operation within a second mode may correspond to that which provides additional/augmented capability and/or functionality with respect to that protocol, standard, and/or recommended practice. Operational modes selectivity may be made between proprietary and non-proprietary modes of operation. All available modulation coding sets (MCSs) may be in employed by providing such multi-mode operation. When operating within one of the operational modes (e.g., proprietary), a signal is generated to include an integer number of data bits per orthogonal frequency division multiplexing (OFDM) symbol using any desired operation (e.g., floor, ceiling, rounding, etc.).

Modulation code set (MCS) and LDPC (low density parity check) coding within multiple user, multiple access, and/or MIMO wireless communications

Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing. In addition, the operational parameter modification can be selective, in that, different modification can be performed to different parameters and/or during different decoding iterations.

Operational parameter adaptable LDPC (low density parity check) decoder

LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.).

LDPC coding systems for 60 GHz millimeter wave based physical layer extension

The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (&#x3b3;) values and check edge message (&#x3bb;) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.

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Lake Oswego, OR, United States of America

Andrew John Blanksby