International Business Machines Corporation

Globalfoundries Inc.

Andrew James Sullivan

Ruchir Puri

Prabhakar Nandavar Kudva

Sharad C Sundararajan

Leon Stok

Charles Jay Alpert

Mahesh A Iyer

Paul Gerard Villarrubia

Minsik Cho

Lakshmi Narasimha Reddy

Robert J Milne

Stephen Thomas Quay

Brian Trevor Denton

Daniel Brand

Jiang Hu

Wilm Ernst Donath

Victor N Kravets

Mihir Choudhury

Rama Gopal Gandham

David John Geiger

Kanad Chakraborty

William E Dougherty

Brent Scott Elmer

Techniques for transforming input operands to reduce overhead for implementing addition operations in hardware are provided. In one aspect, a method for transforming input operands of an adder includes the steps of: receiving a bit array of the input operands; replacing a duplicate signal (e.g., a signal that occurs twice) for a given bit k in the bit array with a single signal at bit k+1; reducing a number of occurrences of the signal on adjacent bits of the input operand, wherein by way of the replacing and reducing a transformed bit array is formed; and providing the transformed bit array to the adder.

Transformation on input operands to reduce hardware overhead for implementing addition

Access is obtained to a truth table having a plurality of rows, each including a plurality of input bits and a plurality of output bits. At least some rows include don't-care inputs. At least some of the rows are clustered into a plurality of multi-row clusters. At least some of the multi-row clusters are assigned to ternary content-addressable memory modules of a prefabricated programmable memory array. Instructions for interconnecting the ternary content-addressable memory modules with a plurality of input pins of the prefabricated programmable memory array and a plurality of output pins of the prefabricated programmable memory array are specified in a data structure, in order to implement the truth table.

Mapping a lookup table to prefabricated TCAMS

Disclosed are a system and method for generating three-dimensional objects to represent files in a three-dimensional environment. A primary classifier classifies stored files into groups based on a first set of properties and generates three-dimensional mesh objects to represent each file. The mesh objects are the same within each group and distinguish the files from group to group. A secondary classifier further classifies each group of files into sub-groups based on a second set of properties and deforms the mesh objects in each sub-group in a particular manner to distinguish files from sub-group to sub-group. Additional classifiers modify the deformed mesh objects to further distinguish files within each sub-group (e.g., by varying the shape, texture, animation, etc.). Each three-dimensional object can then be embedded into a three-dimensional graphical user interface as a selection tool that provides visual cues regarding the contents of a particular file.

Automatic 3D object generation and deformation for representation of data files based on taxonomy classification

A method, apparatus, and computer program product for organizing hierarchical information according to a defined objective.

Method, apparatus and computer program product for organizing hierarchical information

Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design. Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.

Method for optimization of logic circuits for routability

A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.

Method and apparatus for applying fine-grained transforms during placement synthesis interaction

An apparatus and method for determining buffered Steiner trees for complex circuits is provided. The apparatus and method first clusters sinks with similar characteristics such as criticality, polarity and distance. The purpose of this step is to potentially isolate positive sinks from negative ones and non-critical sinks from critical ones. The present invention then constructs low-level Steiner trees over each of these clusters. Finally, a top-level timing driven Steiner tree is computed where each cluster is treated as a sink. The top-level tree is then merged with the low-level trees to yield a solution for the entire net.

Apparatus and method for determining buffered steiner trees for complex circuits

A technology mapping method and device for mapping cost functions on directed acyclic graphs, using decoupled matching and covering and circumventing the memory explosion usually caused by this decoupling. Multiple matches are generated at the head of a wavefront process and embedded within the network. Covering is done at the tail of the wavefront to optimize one or more cost functions.

Wavefront technology mapping

Growing community of inventors

Wappingers Falls, NY, United States of America

Andrew James Sullivan