Analog Devices Global

Analog Devices,inc.

Andrew James Higham

Michael G Perkins

Michael S Allen

Kaushal Sanghai

John L Redford

Boris Lerner

Gregory M Yukna

The present disclosure provides a processor, and associated method, for performing parallel processing within a register. An exemplary processor may include a processing element having a compute unit and a register file. The register file includes a register that is divisible into lanes for parallel processing. The processor may further include a mask register and a predicate register. The mask register and the predicate register respective include a number of mask bits and predicate bits equal to a maximum number of divisible lanes of the register. A state of the mask bits and predicate bits is set to respectively achieve enabling/disabling of the lanes from executing an instruction and conditional performance of an operation defined by the instruction. Further, the processor is operable to perform a reduction operation across the lanes of the processing element and/or generate an address for each of the lanes of the processing element.

Processor architecture and method for simplifying programming single instruction, multiple data within a register

In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.

Interruptible store exclusive

According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Predicate counter

According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

DMA vector buffer

Loop instructions are analyzed and assigned stage numbers based on dependencies between them and machine resources available. The loop instructions are selectively executed based on their stage numbers, thereby eliminating the need for explicit loop set-up and tear-down instructions. On a Single Instruction, Multiple Data machine, the final instance of each instruction may be executed on a subset of the processing elements or vector elements, dependent on the number of iterations of the original loop.

Staged loop instructions

The invention provides a method of processing a sequence of operands to produce compiled code for a target data processor, the method comprising the steps of: automatically analysing a source code to produce a fist representation of that code in single static assignment form; transforming the first representation into a second representation by unlooping &#x3a6; nodes within the single static assignment form so as to create code suitable for tree pattern matching to be performed thereon; performing tree pattern matching on the second representation of the code; and re-looping the &#x3a6; nodes.

Growing community of inventors

Edinburgh, United Kingdom

Andrew James Higham